Abstract: A method and apparatus for measuring alternating current (AC) and direct current (DC) characteristics of a plurality of semiconductor devices. A ring oscillator generates pulses to drive the plurality of semiconductor devices under test. Current/Voltage (IV) and transfer characteristics of the plurality of semiconductor devices are measured using only DC input/output.

Abstract: In a FinFET integrated circuit, the fins are formed with a reduced body thickness in the body area and then thickened in the S/D area outside the body to improve conductivity. The thickening is performed with epitaxial deposition while the lower portion of the gates are covered by a gate cover layer to prevent thickening of the gates at the fin level, which may short the gate to the S/D.

Abstract: A method and apparatus for monitoring a plurality of semiconductor devices is disclosed. At least one array of 2n semiconductor circuits is provided. A clock ring oscillator provides a clock signal. The clock signal drives a frequency divider followed by an n-stage binary counter. The outputs from the counter's stages drive an n-input decoder which sequentially addresses each semiconductor circuit. An output signal from each semiconductor circuit is measured and read out over a common bus, where a distribution of the output signals is a measure of a distribution of a parameter of interest.

Abstract: The present invention is a method and an apparatus for thermo-optic control of optical signals using photonic crystal structures. In one embodiment, a first portion of a split signal is modulated by propagating the signal through a photonic crystal waveguide in which two electrical contacts are laterally spaced from the waveguide region by a plurality of apertures formed through the photonic crystal substrate. A voltage applied across the electrical contacts causes resistive heating of the proximate photonic crystal waveguide through which the signal propagates, thereby modulating the temperature relative to an un-modulated second portion of the split signal that is used as a reference.

Abstract: One embodiment of the present method and apparatus for detecting leaks in a fluid cooling system enables a user to rapidly detect fluid leaks in the vicinity of a microprocessor chip or other delicate item. In one embodiment, the invention comprises a detector and a border coupled to the detector and disposed peripherally about a protected item (e.g., the microprocessor chip or other delicate item). In one embodiment, the border is a layered structure that is adapted to complete an electrical circuit with the detector when the border comes into contact with fluid.

Abstract: Described is an electronic device comprising a junction formed between a first fullerene layer having a first doping concentration and a second fullerene layer having a second doping concentration different from the first doping concentration. The first doping concentration may be zero. The first and/or the second fullerene layer may be a monolayer. The second fullerene layer may comprise an electron donor. One example of such a device is a diode wherein the first fullerene layer is connected to an anode and the second fullerene layer is connected to a cathode. Another example is a field effect transistor wherein the first fullerene layer serves as a gate region and the second fullerene layer serves as a channel region. The second fullerene layer may alternatively comprise an electron acceptor. At least one of the first and second fullerene layers may be formed from C60, or may consist of a single bucky ball.

Abstract: A method for protecting a material of a microstructure comprising said material and a noble metal layer against undesired galvanic etching during manufacture comprises forming on the structure a sacrificial metal layer having a lower redox potential than said material, the sacrificial metal layer being electrically connected to said noble metal layer.

Abstract: A valve comprising a housing having an inlet and spaced therefrom an outlet, a passageway extending between the inlet and the outlet, and a mechanism located in the passageway for controlling the flow of a fluid between the inlet and the outlet, the mechanism including a valve assembly movable between a first open position spaced from a co-operating valve seat and a second closed position at which the valve assembly sealingly engages the valve seat, in which the valve assembly is biased towards the second closed position using a magnet-operated mechanism.

Abstract: A system and method for controlling the rates at which application workload, e.g., TCP connection requests, is admitted to a collection of servers, such as a server farm of an application service provider (ASP) that hosts Internet World Wide Web (WWW) sites of various owners. The system and method are intended to operate in an environment in which each customer has a workload-based SLA for each type of application hosted by the provider and used by the customer. The system and method achieve support (minimum, maximum) TCP connection requests for multiple customers and applications. According to one aspect, the system and method guarantee, control and deliver TCP connection-based workload SLA's to customers whose applications are hosted by the server farm with the use of a workload regulator that operates by regulating only new TCP connection request packets while transparently passing existing TCP connection packets and other request packets received for customers.

Abstract: A highly scalable system and method for supporting (mim,max) based Service Level Agreements (SLA) on outbound bandwidth usage for a plurality of customers whose applications (e.g.,Web sites) are hosted by a server farm that consists of a very large number of servers. The system employs a feedback system that enforces the outbound link bandwidth SLAs by regulating the inbound traffic to a server or server farm. Inbound traffic is admitted to servers using a rate denoted as Rt(i,j), which is the amount of the ith customer's jth type of traffic that can be admitted within a service cycle time to servers which support the ith customer. A centralized device computes Rt(i,j) based on the history of admitted inbound traffic to servers, the history of generated outbound traffic from servers, and the SLAs of various customers. The Rt(i,j) value is then relayed to one or more inbound traffic limiters that regulate the inbound traffic using the rates Rt(i,j) in a given service cycle time.

Abstract: A magnetic memory cell that uses a curved magnetic region to create magnetic anisotropy is provided by the present invention. The magnetic memory cell is created from a free magnetic layer, a barrier layer and a reference magnetic layer. The magnetic layers are constructed such that they have portions that are curved with respect to a first axis and straight with respect to a second perpendicular axis. These curved portions result in a magnetic memory cell that has an easy axis that is parallel to the first axis and a hard axis that is perpendicular to the easy axis. In addition, the resulting magnetic memory cell's coercivity is independent of it's thickness. Thus, the magnetic memory cell is well adapted to being scaled down without increasing the likelihood of thermally induced errors.

Abstract: A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided. The SOI MOSFET device includes a polysilicon back-gate which controls the threshold voltage of a polysilicon-containing front-gate. The back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.

Abstract: The invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by forming an opening into a structure that includes at least a first semiconductor layer and a second semiconductor layer that have different crystal orientations. The opening extends to the first semiconductor layer.

Abstract: A magnetic random access memory circuit comprises a plurality of magnetic memory cells, each of the memory cells including a magnetic storage element having an easy axis and a hard axis associated therewith, and a plurality of column lines and row lines for selectively accessing one or more of the memory cells, each of the memory cells being proximate to an intersection of one of the column lines and one of the row lines. Each of the magnetic memory cells is arranged such that the easy axis is substantially parallel to a direction of flow of a sense current and the hard axis is substantially parallel to a direction of flow of a write current.

Abstract: An optical switch comprises input channels with input optical free-space elements, an intermediate optical free-space element, and input tunable optical lenses with adjustable projection characteristic for projecting lightwaves received from the input optical free-space elements into the intermediate optical free-space element. The switch further comprises output channels with output optical free-space elements, and output tunable optical lenses with adjustable reception characteristic for capturing the lightwave from the intermediate optical free-space element and for feeding the lightwave to the output optical free-space elements. The optical switch can be integrated into a substrate. The tunable lens can be implemented with an individually tunable heater. By adjusting the heaters one can control the projection characteristic of the light beam emitted into a free-space element. Also an asymmetrical switch arrangement is possible.

Abstract: A process for passivating the semiconductor-dielectric interface of a MOS structure to reduce the interface state density to a very low level. A particular example is a MOSFET having a tungsten electrode that in the past has prevented passivation of the underlying semiconductor-dielectric interface to an extent sufficient to reduce the interface state density to less than 5×1010/cm2−eV. Though substantially impervious to molecular hydrogen, thin tungsten layers are shown to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused through a tungsten electrode into an underlying semiconductor-dielectric interface.

Abstract: Described is a device for directing an optical signal from a first optical fiber (101, 102, . . . ) along one of a plurality of selectable switching paths each terminating in a corresponding one of a plurality of second optical fibers (401, 402, . . . ) via an optical element (201, 202, . . . ), the optical element (201, 202, . . . ) being moveable by a controllable actuator (60) from a first to a second position to change the switching path of incident optical signal. The optical element (201, 202, . . . ) is slideably mounted in parallel to a first mounting plate (10) comprising a conduit (11) through which the optical signals from the first optical fiber (101, 102, . . . ) can be directed by the optical element (201, 202, . . . ) along the selected one of the switching paths to one of a plurality of conduits (21) in a second mounting plate (20) parallel to the first mounting plate (10), and further to the corresponding one of second optical fibers (401, 402, . . . ).

Abstract: A method for manufacturing an optical device with a defined total device stress and a therefrom resulting defined birefringence and a therefrom resulting defined optical polarization dependence is disclosed. In a preferred embodiment, a lower cladding layer of an amorphous material with a first refractive index is provided and above that an upper cladding layer of an amorphous material with a second refractive index, which latter is manufactured from a material which is tunable in its stress. Between the lower and upper cladding layer an optical waveguide core is manufactured comprising an amorphous material having a third refractive index which is larger than the first and second refractive index. The optical waveguide core is thermally annealed, after which it has a defined waveguide core stress. The upper cladding layer is manufactured to have a cladding layer stress that together with the waveguide core stress results in the total device stress.

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches.

Abstract: A write circuit for selectively writing one or more magnetic memory cells in an MRAM includes at least one programmable current source being couplable to one or more global word lines in the MRAM, the programmable current source including an input for receiving a first control signal and an output, the programmable current source generating at least a portion of a write current at the output having a magnitude which varies in response to the first control signal. The write circuit further includes a plurality of current sinks, each current sink being couplable to one or more global word lines in the MRAM, each current sink including an input for receiving a second control signal, each current sink returning at least a portion of the write current in response to the second control signal.