Abstract: This invention describes a new method for forming and depositing thin films of crystalline dielectric materials. The present technique uses chemical synthesis to control the granularity and thickness of the dielectric films. This method has several key advantages over existing technologies, and facilitates the integration of crystalline dielectric materials into high-density memory devices.

Abstract: The present invention relates to a novel organosilicon particle having the formula SiaObCcHd. The particle may be coated with an organic film, preferably a rigid connector compound. The present invention also provides a method of using the organosilicon particle and/or rigid connector compound in the formation of a low-k dielectric film.

Abstract: A complementary metal oxide semiconductor (CMOS) device having silicide contacts that are self-aligned to deep junction edges formed within a surface of a semiconductor substrate as well as a method of manufacturing the same are disclosed. Specifically, the CMOS device includes a plurality of patterned gate stack regions formed on a surface of a semiconductor substrate. Each plurality of patterned gate stack regions includes an L-shaped nitride spacer formed on exposed vertical sidewalls thereof, the L-shaped nitride spacer having a vertical element and a horizontal element, wherein the horizontal element is formed on a portion of the substrate that abuts each patterned gate stack region. Silicide contacts are located on other portions of the semiconductor substrate between adjacent patterned gate stack regions not containing the horizontal element of the L-shaped nitride spacer.

Abstract: A memory storage device is provided that includes a storage cell having a changeable magnetic region. The changeable magnetic region includes a material having a magnetization state that is responsive to a change in temperature. The memory storage device also includes a heating element. The heating element is proximate to the storage cell for selectively changing the temperature of the changeable magnetic region of said storage cell. By heating the storage cell via the heating element, as opposed to heating the storage cell by directly applying current thereto, more flexibility is provided in the manufacture of the storage cells.

Abstract: A method (and resultant structure) for forming a metal silicide contact on a silicon-containing region having controlled consumption of said silicon-containing region, includes implanting Ge into the silicon-containing region, forming a blanket metal-silicon mixture layer over the silicon-containing region, reacting the metal-silicon mixture with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal-silicon mixture layer, forming a blanket silicon layer over the metal silicon alloy layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.

Abstract: A system and method of improving the accessibility of Web sites and pages through the use of accessibility descriptors that can be assigned to a Web site and/or each page of a Web site. The descriptors enable the page(s) of the site to be assessed and then displayed according to a particular user's needs, or if appropriate may notify the user if a page cannot be used or rendered more accessible. The system can be set up to require a user fee for the service, thus encouraging Web creators to design Web pages that can be modified in accordance with the accessibility descriptors.

Abstract: A capacitor structure characterized by improved capacitance as a result of increasing the capacitance associated with charge spreading that occurs within the electrodes of the capacitor. The electrodes are formed of superconducting or high-dielectric constant conductor materials, and are preferably used in combination with high-dielectric constant insulator materials. The capacitor structures are particularly suited as thin-film capacitors of the type used for high-density applications such as DRAM.

Abstract: The present invention provides a method for fabricating sub-0.05 &mgr;m double-gated MOSFET devices utilizing a damascene-gate process. The damascene-gate process provides sub-0.05 &mgr;m double-gated MOSFET devices which include a frontside poly gate electrode and a backside implant region. The two gates are separated by two gate dielectrics that include a thin (on the order of about 200 Å or less) Si layer which is sandwiched between the gate dielectrics. The Si layer serves as the channel region of the device. Short-channel effects are greatly suppressed in the present double-gate MOSFET device because the two gates terminate the drain filed lines, preventing the drain potential from being felt at the source end of the channel.

Abstract: A laminar structure upon a substrate is formed from a) a lattice layer comprising DNA (deoxyribonucleic acid) segments arranged to form cells of the lattice layer, and b), at least one nanoparticle being disposed within each cell of the lattice layer. The nanoparticles are preferably of substantially uniform diameter not exceeding 50 nanometers. A coating may be applied to adhere the the particles to the substrate and to maintain their substantially uniform spaced-apart relationship. The DNA lattice layer is fabricated using known automated synthetis methods, and is designed to contain specific nucleotide base sequences which cause the DNA to form an ordered array of openings, or lattice cells, by self-assembly. Self-assembly of the DNA lattice may be at an air-liquid interface, or in solution. A preferred embodiment is a magnetic storage medium in which the particles are magnetic particles with diameters in the range of 5-20 nm.

Abstract: A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. In accordance with the method of the present invention, at least one dummy gate region is first formed atop an SOI layer. The dummy gate region includes at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of the sacrificial polysilicon region. Next, an oxide layer that is coplanar with an upper surface of the dummy gate region is formed and then the sacrificial polysilicon region is removed to expose a portion of the SOI layer. A thinned device channel region is formed in the exposed portion of the SOI layer and thereafter inner nitride spacers are formed on exposed walls of the fist nitride spacers. Next, a gate region is formed over the thinned device channel region and then the oxide layer is removed so as to expose thicker portions of the SOI layer than de device channel region.

Abstract: The present invention provides a method for fabricating low-resistance, sub-0.1 &mgr;m channel T-gate MOSFETs that do not exhibit any poly depletion problems. The inventive method employs a damascene-gate processing step and a chemical oxide removal etch to fabricate such MOSFETs. The chemical oxide removal may be performed in a vapor containing HF and NH3 or a plasma containing HF and NH3.

Abstract: A semiconductor device comprising a gate having an approximately 0.05 &mgr;m channel length, an oxide layer below the gate, a self-aligned compensation implant below the oxide layer, a halo implant surrounding the self-aligned compensation implant below the oxide layer; and gate and drain regions on opposite sides of the halo implant and below the oxide layer.

Abstract: A method and structure for an integrated circuit structure that includes introducing precursors on a substrate, oxidizing the precursors and heating the precursors. The introducing and the oxidizing of the precursors is preformed in a manner so as to form an amorphous glass dielectric on the substrate. The process preferably includes, before introducing the precursors on the substrate, cleaning the substrate.

Abstract: A technique for forming a sub-0.05 &mgr;m channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the fabrication of a MOSFET device with double-gate/double channel structure. The gates are present on opposite sides of a silicon film having a vertical thickness of about 80 nm or less which is present in the gate region. The silicon film serves as the vertical channel regions of the structure and connects diffusion regions that are abutting the gate region to each other. In the inventive device, the current is double that of a conventional planar MOSFET with the same physical width due to its dual channel feature.

Abstract: A MOS structure processed to have a semiconductor-dielectric interface that is passivated to reduce the interface state density. An example is a MOSFET having a gate dielectric on which an electrode is present that is substantially impervious to molecular hydrogen, but sufficiently thin to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused therethrough into an underlying semiconductor-dielectric interface. Atomic hydrogen diffusion can be achieved by subjecting such an electrode to hydrogen plasma, forming the electrode of an aluminum-tungsten alloy in the presence of hydrogen, and implanting atomic hydrogen into the electrode. The latter two techniques are each followed by an anneal to cause the atomic hydrogen to diffuse through the electrode and into the semiconductor-dielectric interface.

Abstract: The present invention relates to a novel organosilicon particle having the formula SiaObCcHd. The particle may be coated with an organic film, preferably a rigid connector compound. The present invention also provides a method of using the organosilicon particle and/or rigid connector compound in the formation of a low-k dielectric film.

Abstract: A gas mixture comprised of nitric oxide and one or more impurities selected from nitrous oxide, nitrogen dioxide, nitrous acid, sulfur dioxide, carbonyl sulfide, water vapor and carbon dioxide is purified by pressure swing adsorption or temperature swing adsorption using a porous, metal-free polymer adsorbent that does not promote the disproportionation of nitric oxide to nitrogen dioxide and nitrogen or nitrous oxide. The adsorption step is preferably carried out at tempereatures in the range of about −120 to about 0° C.

Abstract: A process and apparatus for recovering sulphur from a combustible gas stream comprising hydrogen sulphide, air, commercially pure oxygen or oxygen-enriched air. The combustible gas stream are fed to a burner which fires into an elongate furnace. A longitudinally extending flame is created which as a relatively oxygen-poor endothermic hydrogen sulphide dissociation region, and a relatively oxygen-rich, intense hydrogen sulphide combustion region. Residual hydrogen sulphide reacts with sulphur dioxide formed by the combustion to produce sulphur vapor. The furnace has an aspect ratio of about 8:1. The flame diverges from its root to occupy at its maximum cross-sectional area at least about 80% of the cross-sectional area of the furnace interior coplanar therewith.

Abstract: An apparatus for use on board ship to reliquefy a compressed vapour employs pre-assemblies of components. The reliquefaction is effected in a closed cycle in which a working fluid is compressed in at least one compressor, is cooled in a first heat exchanger, is expanded in a turbine and is warmed in a second heat exchanger in which the compressed vapour is at least partially condensed. The apparatus comprises a first pre-assembly including the second heat exchanger and a second pre-assembly including the first heat exchanger, the compressor and the expansion turbine are positioned. The pre-assemblies are positioned on respective platforms.

Abstract: The present invention provides a structured packing comprising a plurality of corrugated sheets and a plurality of flat, planar members alternating with and located between the sheets to inhibit turbulence in vapor ascending through the structured packing. The plurality of planar members are positioned so that at least the lowermost horizontal edge of the planar members and the corrugated sheets are situated proximal to one another as viewed when said structured packing is in use. When the planar members have substantially the same length and width as the corrugated sheets, the planar members and the corrugated sheets have perforations sized to inhibit transverse liquid and vapor flow while but allowing transverse pressure equalization through the structured packing. The size and number of perforations can be optimized for air separation applications.