Abstract: A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided. The SOI MOSFET device includes a polysilicon back-gate which controls the threshold voltage of a polysilicon-containing front-gate. The back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.

Abstract: The invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by forming an opening into a structure that includes at least a first semiconductor layer and a second semiconductor layer that have different crystal orientations. The opening extends to the first semiconductor layer.

Abstract: A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided in which an implanted back-gate is formed into a Si-containing layer of an SOI wafer. The implanted back-gate thus formed is capable of controlling the threshold voltage of a polysilicon-containing front-gate which is formed over a portion of the implanted back-gate region. The implanted back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.

Abstract: An optical switch comprises input channels with input optical free-space elements, an intermediate optical free-space element, and input tunable optical lenses with adjustable projection characteristic for projecting lightwaves received from the input optical free-space elements into the intermediate optical free-space element. The switch further comprises output channels with output optical free-space elements, and output tunable optical lenses with adjustable reception characteristic for capturing the lightwave from the intermediate optical free-space element and for feeding the lightwave to the output optical free-space elements. The optical switch can be integrated into a substrate. The tunable lens can be implemented with an individually tunable heater. By adjusting the heaters one can control the projection characteristic of the light beam emitted into a free-space element. Also an asymmetrical switch arrangement is possible.

Abstract: A method and structure that forms a multilayer nanoparticle thin film assembly begins by functionalizing a substrate with functional molecules. Next, the invention replaces a stabilizer on a bottom surface of the first nanoparticles with the functional molecules via surface ligand exchange to make a first nanoparticle layer on the substrate. The invention then replaces the stabilizer on a top surface of the first nanoparticle layer with functional molecules via surface ligand exchange. The invention replaces the stabilizer on a bottom surface of the second nanoparticles with the functional molecules via surface ligand exchange to make a second nanoparticle layer on the first nanoparticle layer. Lastly, the invention repeats the previous steps and forms additional nanoparticle layers.

Abstract: A process for passivating the semiconductor-dielectric interface of a MOS structure to reduce the interface state density to a very low level. A particular example is a MOSFET having a tungsten electrode that in the past has prevented passivation of the underlying semiconductor-dielectric interface to an extent sufficient to reduce the interface state density to less than 5×1010/cm2−eV. Though substantially impervious to molecular hydrogen, thin tungsten layers are shown to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused through a tungsten electrode into an underlying semiconductor-dielectric interface.

Abstract: A method (and resultant structure) of forming a semiconductor device, includes forming a metal-back-gate over a substrate and a metal back-gate, forming a passivation layer on the metal back-gate to prevent the metal back-gate from reacting with radical species, and providing an intermediate gluing layer between the substrate and the metal back-gate to enhance adhesion.

Abstract: Described is a device for directing an optical signal from a first optical fiber (101, 102, . . . ) along one of a plurality of selectable switching paths each terminating in a corresponding one of a plurality of second optical fibers (401, 402, . . . ) via an optical element (201, 202, . . . ), the optical element (201, 202, . . . ) being moveable by a controllable actuator (60) from a first to a second position to change the switching path of incident optical signal. The optical element (201, 202, . . . ) is slideably mounted in parallel to a first mounting plate (10) comprising a conduit (11) through which the optical signals from the first optical fiber (101, 102, . . . ) can be directed by the optical element (201, 202, . . . ) along the selected one of the switching paths to one of a plurality of conduits (21) in a second mounting plate (20) parallel to the first mounting plate (10), and further to the corresponding one of second optical fibers (401, 402, . . . ).

Abstract: An integrated circuit structure is disclosed that comprises a pair of capacitors, each having metal plates separated by an insulator, and metal gate semiconductor transistors electrically connected to the capacitors. The metal gate of the transistors and one of the metal plates of each of the capacitors comprise the same metal level in the integrated circuit structure. More specifically, each of the capacitors comprise a vertical capacitor having an upper metal plate vertically over a lower metal plate and each metal gate of the transistors and each upper metal plate of the capacitors comprise the same metal level in the integrated circuit structure.

Abstract: A method for manufacturing an optical device with a defined total device stress and a therefrom resulting defined birefringence and a therefrom resulting defined optical polarization dependence is disclosed. In a preferred embodiment, a lower cladding layer of an amorphous material with a first refractive index is provided and above that an upper cladding layer of an amorphous material with a second refractive index, which latter is manufactured from a material which is tunable in its stress. Between the lower and upper cladding layer an optical waveguide core is manufactured comprising an amorphous material having a third refractive index which is larger than the first and second refractive index. The optical waveguide core is thermally annealed, after which it has a defined waveguide core stress. The upper cladding layer is manufactured to have a cladding layer stress that together with the waveguide core stress results in the total device stress.

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches.

Abstract: A semiconductor structure (and method for forming) having transistors having both metal gates and polysilicon gates on a single substrate in a single process is disclosed. The method forms a gate dielectric layer on the substrate and forms the metal seed layer on the gate oxide layer. The method patterns the metal seed layer to leave metal seed material in metal gate seed areas above the substrate. Next, the method patterns a polysilicon layer into polysilicon structures above the substrate. Some of the polysilicon structures comprise sacrificial polysilicon structures on the metal gate seed areas and the remaining ones of the polysilicon structures comprise the polysilicon gates. The patterning of the polysilicon gates forms the sacrificial gates above all the metal gate seed areas. Following that, the invention forms sidewall spacers, and source and drain regions adjacent the polysilicon structures.

Abstract: A write circuit for selectively writing one or more magnetic memory cells in an MRAM includes at least one programmable current source being couplable to one or more global word lines in the MRAM, the programmable current source including an input for receiving a first control signal and an output, the programmable current source generating at least a portion of a write current at the output having a magnitude which varies in response to the first control signal. The write circuit further includes a plurality of current sinks, each current sink being couplable to one or more global word lines in the MRAM, each current sink including an input for receiving a second control signal, each current sink returning at least a portion of the write current in response to the second control signal.

Abstract: A method for manufacturing an optical device with a defined total device stress, birefringence and optical polarization dependence is disclosed. The method comprises first providing a tower cladding layer of an amorphous material with a first refractive index and then providing above the lower cladding layer an upper cladding layer of an amorphous material with a second refractive index. An optical waveguide core comprising an amorphous material having a third refractive index (larger than the first refractive index and the second refractive index) is provided between the lower and the upper cladding layers. The upper cladding layer is thermally annealed by keeping the upper cladding layer at a first temperature, then raising the temperature to a second temperature, maintaining the second temperature for an annealing time period, and lowering the temperature to a third temperature, after which the temperature is lowered to a fourth temperature.

Abstract: An electrically tunable coupler device is disposed on a substrate comprising a first and a second waveguide, for guiding optical signals. The coupler device comprises a heater element disposed adjacent the first waveguide for thermo-optically shifting the phase of the optical signal in the first waveguide in response to a control voltage applied to the heater element. The heater element is disposed in an interaction region of the optical signals, such that, within the interaction region, a temperature gradient across the first and the second waveguide is generated in dependence on the applied control voltage. A heat sink element can be disposed adjacent the second waveguide to absorb thermal energy from the heater element. This device can be fabricated at reduced cost and in increased packing density and is usable e.g. in directional couplers, Mach-Zehnder interferometers, optical ring resonators, IIR filters, or optical modulators.

Abstract: A double-gate field effect transistor (DGFET) is provided using a damascene-like replacement gate processing step to create sidewall source/drain regions, oxide spacers and gate structures inside a previously formed trench. The damascene-like replacement gate processing step allows for the fabrication of a tapered transistor body region having a thicker body under the contacts which reduces access resistance.

Abstract: A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.

Abstract: The present invention is directed to a microelectric device and especially a Field effect transistor comprising a source, drain, channel, an insulating layer overlying said channel containing at least one closed cage molecule, said closed cage molecule being capable of exhibiting a Coulomb blockade effect upon application of a voltage between said source and drain. Two different microelectronic devices are described containing the closed cage molecule, a logic cell and a memory cell.

Abstract: A high efficiency light emitting diode (LED) driver circuit utilizes a capacitor to regulate the LED driving current. The voltage across the capacitor is monitored to maintain a preselected low threshold voltage on the capacitor, which determines the LED optical emission intensity. The capacitor provides the LED driver current by discharging through the LED during transmission intervals, and the power supply for the device is used only to maintain the capacitor charge level. The LED driver circuit accordingly operates at high efficiency with low power consumption. The LED driver current can be regulated by changing the low and high threshold voltages of the capacitor pump controller, thereby to control the optical intensity of the LED.

Abstract: A process for making abrupt, e.g. <20 nm/decade, PN junctions and haloes in, e.g., CMOSFETs having gate lengths of, e.g. <50 nm, uses a mask, e.g., sidewall spacers, during ion implantation of gate, source, and drain regions. The mask is removed after source-drain activation by annealing and source and drain extension regions are then implanted. Then the extension regions are activated. Thereafter halo regions are implanted and activated preferably using spike annealing to prevent their diffusion. The process can also be used to make diodes, bipolar transistors, etc. The activation annealing steps can be combined into a single step near the end of the process.