Patents Represented by Attorney, Agent or Law Firm Ware & Freidenrich
  • Patent number: 6780600
    Abstract: Disclosed are nucleotide coding sequences and polypeptide sequences for synaptic activation binding proteins that are characterized by induction in the central nervous system following neuronal activity in rat hippocampus. Such proteins are identified by (i) substantial homology at the nucleotide or protein sequence level to specifically defined rat, human or mouse coding sequences or proteins, (ii) ability to bind to and affect the activity of effector proteins in the CNS, such as metabotropic glutamate receptors, (iii) binding specificity for a particular binding sequence, and (iv) presence in the sequence of a PDZ-like domain. Nucleotides and polypeptides of the invention are useful in screening and diagnostic assays.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: August 24, 2004
    Assignee: The Johns Hopkins University School of Medicine
    Inventors: Paul F. Worley, Paul R. Brakeman
  • Patent number: 6777260
    Abstract: A method of forming sub-lithographic sized contact holes in semiconductor material, which includes forming layers of etch mask materials, and forming intersecting first and second trenches in the etch mask layers, where through-holes are formed completely through the etch mask layers only where the first and second trenches intersect. The first and second trenches are made by the formation and subsequent removal of very thin vertical layers of material. The width dimensions of the trenches, and therefore of the through-holes, are sub-lithographic because they are dictated by the thickness of the thin vertical layers of material, and not by conventional photo lithographic processes used to form those vertical layers of material. The sub-lithographic through-holes are then used to etch sub-lithographic sized contact holes in underlying semiconductor materials.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: August 17, 2004
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Bomy Chen
  • Patent number: 6779167
    Abstract: An automated wiring pattern layout method is provided. With this method, a first wiring pattern is generated with width W and extending in a first direction, and a second wiring pattern is generated with width W and extending in a direction perpendicular to the first wiring pattern in a manner such that the end thereof ends at the end portion of the first wiring pattern. Moreover, an overlapping region is generated by bending an end of either one of the first or the second wiring pattern at a right angle to produce an L-shaped extension and overlaying the first and the second wiring pattern, and a rectangular-shaped VIA pattern is generated at the overlapping region.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: August 17, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mutsunori Igarashi, Masaaki Yamada, Koji Hashimoto, Makoto Takashima, Atsuhiko Ikeuchi
  • Patent number: 6777405
    Abstract: Duplex polynucleotides containing damage or errors are detected with hindered intercalating compounds which are capable of intercalating only in the presence of such damage or error. Conditions characterized by the presence of polynucleotide errors or damage are treated with such compounds that are capable of catalyzing polynucleotide cleavage with light.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: August 17, 2004
    Assignee: California Institute of Technology
    Inventors: Jacqueline K. Barton, Brian A. Jackson, Brian P. Hudson
  • Patent number: 6777966
    Abstract: The cleaning device may clean probe elements. The probe elements may be the probe elements of a probe card testing apparatus for testing semiconductor wafers or semiconductor dies on a semiconductor wafer or the probe elements of a handling/testing apparatus for testing the leads of a packaged integrated circuit. During the cleaning of the probe elements, the probe card or the handler/tester is cleaned during the normal operation of the testing machine without removing the probe card from the prober. The cleaning device may be placed within the prober or tester/handler similar to a wafer containing semiconductor dies to be tested so that the probe elements of the testing machine contact the cleaning medium periodically to remove debris and/or reshape the tips of the probe elements.
    Type: Grant
    Filed: July 24, 2000
    Date of Patent: August 17, 2004
    Assignee: International Test Solutions, Inc.
    Inventors: Alan E. Humphrey, Billie Jean Freeze
  • Patent number: 6777999
    Abstract: In a master block, the exponential conversion characteristic is determined on the basis of a common mode reference voltage and a reference voltage. In a slave block, the exponential conversion characteristic determined with the master block is used to create a control voltage and a gain control signal on the basis of a common mode reference voltage and a reference voltage. For example, a gain of the variable gain amplifier is controlled by using this gain control signal.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: August 17, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuo Kanou, Takafumi Yamaji, Tetsuro Itakura
  • Patent number: 6775193
    Abstract: The present invention provides a system and method for testing embedded memories. The present invention logically combines many different embedded memories into one or more large, virtual memory blocks in order to test multiple memories together. The invention defines the X and/or Y address space in all memories in order to cover all memories combined. Compare circuits associated with each memory module are used to compare the data output from each memory cell to an expected value (e.g., to a value that would be expected if the memory cell was operating properly). The invention further uses mask logic to “mask out” any unimplemented address space in each individual memory. The mask logic will always indicate that the comparison or memory test passed when unimplemented addresses are selected. The results of the comparison may be bundled and multiplexed to a test input/output port.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: August 10, 2004
    Assignee: GIGA Semiconductor, Inc.
    Inventors: Taiching Shyu, Lee-Lean Shu
  • Patent number: 6774333
    Abstract: A method, apparatus, and system for optically sorting and/or manipulating carbon nanotubes by creating an optical dipole trap with a focused light source (e.g., a laser) are described in detail herein. In one representative embodiment, light from the light source may be directed onto a mixture of carbon nanotubes, the mixture including a target class of carbon nanotubes having dimensions (e.g., length and diameter) corresponding to particular electronic properties suitable for an application. By identifying a resonant condition corresponding to the target class of carbon nanotubes, and tuning the light source substantially to the resonant condition, an optical dipole trap may be created to attract carbon nanotubes of the target class to allow manipulation and/or sorting of the target class of carbon nanotubes from the mixture, or rotation of the nanotubes via rotation of a plane of polarization of the light, in an embodiment.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: August 10, 2004
    Assignee: Intel Corporation
    Inventor: Eric C. Hannah
  • Patent number: 6773897
    Abstract: The present invention provides methods relating to chemotherapeutic treatment of a cell proliferative disorder. In particular, a method is provided for predicting the clinical response to certain types of chemotherapeutic agents. Alkylating agents, used for the treatment of certain types of tumors including tumors of the nervous system and lymph system, are efficacious agents when the damage they do to tumor cell DNA is not repaired by cellular DNA repair mechanisms. The present invention provides a method for determining the activity of a gene encoding a DNA repair enzyme, thus providing a prediction of the clinical response to alkylating agents.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: August 10, 2004
    Assignee: The Johns Hopkins University School of Medicine
    Inventors: James G. Herman, Stephen B. Baylin, Manel Esteller
  • Patent number: 6773989
    Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indentations. The trenches are filled with a conducting material to form blocks of the conducting material that constitute control gates. The trench indentations result in the formation of protruding portions on the control gates that extend over the floating gates.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: August 10, 2004
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Chih Hsin Wang
  • Patent number: 6773974
    Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array. The array includes word lines and source lines that connect together control gates and source regions from memory cells contained in row within the array. The strap regions include word line strap cells through which the word lines traverse, wherein the word lines completely traverse across the strap regions, and source line strap cells in which the source lines terminate without completely traversing across the strap region. A first plurality of conductive metal contacts are each connected to one of the word lines in one of the word line strap cells. A second plurality of conductive metal contacts are each connected to one of the source lines in one of the source line strap cells.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: August 10, 2004
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Chih Hsin Wang, Amitay Levi
  • Patent number: 6771819
    Abstract: A system and method for object inspection that includes an image recognition program stored on a tangible medium for classifying and subclassifying regions of interest on an image. The image recognition program can be used in an image inspection system to determine defects on objects such as printed wiring assemblies. The image recognition program is executable to collect raw image data, segment out rectangular regions of interest that can be component sites defined by CAD data, preprocess each region of interest by scaling, gain and offset correction, and gamma correction, generating a set of image spaces for each region of interest using a set of spatial image transforms, generating features on the image spaces, scoring the features, comparing the feature scores to a knowledge base of feature scores to make a class determination for the features, generating a presence/absence decision confidence for the features, calculating a class determination and decision confidence for each region of interest.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: August 3, 2004
    Assignee: Intelligent Reasoning Systems, Inc.
    Inventors: Mark R. DeYong, Jeff E. Newberry, John W. Grace, Thomas C. Eskridge
  • Patent number: 6770021
    Abstract: A neutron source for neutron brachytherapy is disclosed that may generate neutrons to treat cancer and other tumors. The neutron source in accordance with the invention may include a capsule into which the neutron emitting material is loaded and a guide wire. A coiled wire may be placed around the capsule and the guide wire to strengthen the capsule and guide wire. In accordance with one embodiment, the capsule containing the neutron emitting material is sufficiently thin so that the helium gas generated during the decay of the neutron emitting material may escape into the atmosphere. In a preferred embodiment, the neutron emitting material may be Californium (Cf225).
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: August 3, 2004
    Assignee: Isotron, Inc.
    Inventor: David Halpern
  • Patent number: 6770822
    Abstract: A high frequency device packing method and package are described wherein coaxial structures are formed from the high frequency device to the via. A coaxial via structure and a micro-coaxial bonding wire are described.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: August 3, 2004
    Assignee: Bridgewave Communications, Inc.
    Inventors: Eliezer Pasternak, Sean Cahill, Bance Hom
  • Patent number: 6768745
    Abstract: A SONET network interface for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) to enable transmission of signals therebetween. The interface having: a common bus of predetermined bit width for interfacing the HSU unit with each of the LSU units to enable transmission of signals from each of the LSUs to the HSU, and reception of the signals from the HSU to each of the LSUs; a first partition bus of the predetermined bit width for interfacing the HSU to a predetermined number of the LSUs, the first partition bus being partitioned into a first bus for interfacing the HSU to a first subset of the LSUs and a second bus for interfacing the HSU to a second subset of the LSUs; and a second partition bus of the predetermined bit width for interfacing the HSU to a predetermined number of the LSU units.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: July 27, 2004
    Assignee: Zhone Technologies, Inc.
    Inventors: Steven Scott Gorshe, Robert Wesley Brooks
  • Patent number: 6768961
    Abstract: A system and method for analyzing error information from a semiconductor fabrication process. The system receives wafer map data describing a plurality of failing chips on a particular semiconductor wafer. The system utilizes the wafer map data to classify each of the failing chips into one of several error categories, such systematic errors, repeated or reticle errors, and random errors. The system further partitions the systematic errors into spatial clusters, which may be compared against a known library of spatial error patterns for identifying the origins of the systematic errors.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: July 27, 2004
    Assignee: Yield Dyamics, Inc.
    Inventors: Jonathan B. Buckheit, Weidong Wang
  • Patent number: D493836
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: August 3, 2004
    Assignee: Accessories Marketing, Inc.
    Inventors: Steve Cegelski, Rodney Cegelski
  • Patent number: D493985
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: August 10, 2004
    Assignee: Wonderland Nursery Goods Co., Ltd.
    Inventor: Shun-Min Chen
  • Patent number: D494199
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: August 10, 2004
    Assignee: Gemological Institute of America, Inc.
    Inventor: Sherman Gingerella
  • Patent number: D494393
    Type: Grant
    Filed: January 7, 2004
    Date of Patent: August 17, 2004
    Assignee: Wonderland Nursery Goods Co., Ltd.
    Inventor: Shun-Min Chen