Patents Represented by Attorney, Agent or Law Firm Warren L. Franz
  • Patent number: 8344479
    Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: January 1, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Robert L. Pitts, Greg C. Baldwin
  • Patent number: 8343805
    Abstract: A method and structure for uncovering captive devices in a bonded wafer assembly comprising a top wafer and a bottom wafer. One embodiment method includes forming a plurality of cuts in the top wafer and removing a segment of the top wafer defined by the plurality of cuts. The bottom wafer remains unsingulated after the removal of the segment.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: January 1, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Clayton Lee Stevenson, Jason C. Green, Daryl Ross Koehl, Buu Quoc Diep
  • Patent number: 8338208
    Abstract: A MEMS may integrate movable MEMS parts, such as mechanical elements, flexible membranes, and sensors, with the low-cost device package, leaving the electronics and signal-processing parts in the integrated circuitry of the semiconductor chip. The package may be a leadframe-based plastic molded body having an opening through the thickness of the body. The movable part may be anchored in the body and extend at least partially across the opening. The chip may be flip-assembled to the leads to span across the foil, and may be separated from the foil by a gap. The leadframe may be a prefabricated piece part, or may be fabricated in a process flow with metal deposition on a sacrificial carrier and patterning of the metal layer. The resulting leadframe may be flat or may have an offset structure useful for stacked package-on-package devices.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: December 25, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Edgar Rolando Zuniga-Ortiz, William R. Krenik
  • Patent number: 8304303
    Abstract: Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Sameer Pendharkar
  • Patent number: 8304274
    Abstract: Semiconductor-centered MEMS (100) integrates the movable MEMS parts, such as mechanical elements, flexible membranes, and sensors, with the low-cost device package, and leaving only the electronics and signal-processing parts in the integrated circuitry of the semiconductor chip. The package is substrate-based and has an opening through the thickness of the substrate. Substrate materials include polymer tapes with attached metal foil, and polymer-based and ceramic-based multi-metal-layer dielectric composites with attached metal foil. The movable part is formed from the metal foil attached to a substrate surface and extends at least partially across the opening. The chip is flip-assembled to span at least partially across the membrane, and is separated from the membrane by a gap.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Edgar Rolando Zuniga-Ortiz, William R. Krenik
  • Patent number: 8305385
    Abstract: A display device with embedded networking capability is described herein. The display device uses at least a portion of a memory of the display device, the memory of which is used for storing video/image data in the display, to store networking codes for establishing and maintaining the network connection.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Umesh G Jani, Anne E French
  • Patent number: 8304342
    Abstract: A chemical mechanical polishing (CMP) stop layer is implemented in a semiconductor fabrication process. The CMP stop layer, among other things, mitigates erosion of sidewall spacers during semiconductor fabrication and adverse effects associated therewith.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Michael Francis Pas, Manfred Ramin
  • Patent number: 8304333
    Abstract: A method for manufacturing a semiconductor device includes forming a gate electrode over a gate dielectric. The gate dielectric is formed by forming a lanthanide metal layer over a nitrided silicon oxide layer, and then performing an anneal to inter-diffuse atoms to form a lanthanide silicon oxynitride layer. A gate electrode layer may be deposited before or after the anneal. In an embodiment, the gate electrode layer includes a non-lanthanide metal layer, a barrier layer formed over the non-lanthanide metal layer, and a polysilicon layer formed over the barrier layer. Hafnium atoms may optionally be implanted into the nitrided silicon oxide layer.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
  • Patent number: 8305666
    Abstract: System and method for maintaining perceived hue constancy. A method for displaying an image includes receiving a color vector and associated image data, remapping the color vector to maintain a perceived hue constancy by adjusting a hue component of the color vector in response to a change in a lightness component or a chroma component of the color vector, providing the remapped color vector to a light source for display, and displaying image data associated with the color vector. The use of the constant hue curve ensures that the adjusting of the color vector maintains the perceived hue of the color vector, thereby helping to maintain image quality.
    Type: Grant
    Filed: February 5, 2011
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Rajeev Ramanath
  • Patent number: 8304846
    Abstract: An integrated circuit containing a capacitive microphone with a back side cavity located within the substrate of the integrated circuit. Access holes may be formed through a dielectric support layer at the surface of the substrate to provide access for etchants to the substrate to form the back side cavity. The back side cavity may be etched after a fixed plate and permeable membrane of the capacitive microphone are formed by providing etchants through the permeable membrane and through the access holes to the substrate.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Wei-Yan Shih
  • Patent number: 8305722
    Abstract: A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e.g.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: November 6, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Albert Z. H. Wang, Chen H. Tsay, Peter Deane
  • Patent number: 8304320
    Abstract: An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is then more lightly doped than, and defined with dopant of higher atomic weight, than the lateral extension of the drain.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: November 6, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Sandeep R. Bahl, William D. French, Constantin Bulucea
  • Patent number: 8306350
    Abstract: According to one embodiment of the invention, a method is provided for aspect ratio distortion minimization. The method includes receiving input pixels from a video source. The method then determines an input position and scale factor for each input pixel. A count value determines that a pixel should be outputted. A polyphase finite impulse response filter is centered on a particular input pixel based on the count value. An output pixel is generated using the polyphase finite response filter on a particular input pixel based on the count value and output pixels are outputted.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Jeffrey M. Kempf
  • Patent number: 8304263
    Abstract: A test circuit for measuring a gate delay as a function of stress is disclosed. The test circuit includes an oscillator, a reference gate chain, a test gate chain, and a counter. The counter measures the difference in propagation delay between the test chain and the reference chain in calibrated oscillator cycles. Differences in test gate delay as a function of applied stress may be measured within the calibration accuracy of the oscillator frequency. The use of the reference gate chain allows a simpler unipolar counter.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Andrew Marshall
  • Patent number: 8304835
    Abstract: A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: November 6, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, Sandeep R. Bahl, William D. French, Jeng-Jiun Yang, Donald M. Archer, D. Courtney Parker, Prasad Chaparala
  • Patent number: 8306804
    Abstract: A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Gianluca Boselli, Jonathan S. Brodsky, John E. Kunz, Jr.
  • Patent number: 8306075
    Abstract: A system and method for optical frequency conversion having asymmetric output include a coherent light apparatus. The coherent light apparatus includes a coherent light source that produces a first coherent light, a frequency converter optically coupled to the coherent light source, and a coupling optic optically coupled between the coherent light source and the frequency converter. The frequency converter converts the first coherent light to a second coherent light at a second frequency and includes an asymmetric frequency converter (AFC) that nonlinearly converts the first coherent light to the second coherent light with the frequency conversion being more efficient in a first direction than in a second direction. A resonant cavity formed about the AFC circulates the first coherent light and transmits the second coherent light propagating in the first direction.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Gregory A. Magel
  • Patent number: 8305395
    Abstract: In a method embodiment, a method for image processing includes receiving one or more signals indicative of an optical characteristic of one or more respective light beams. A transform is generated based on the received one or more signals. The transform converts a first plurality of image components encoded by a first plurality of colors to a second plurality of image components encoded by a second plurality of colors.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Rajeev Ramanath, Takeshi Honzawa
  • Patent number: 8304308
    Abstract: A semiconductor structure contains a bipolar transistor (101) and a spacing structure (265-1 or 265-2). The transistor has an emitter (241), a base (243), and a collector (245). The base is formed with an intrinsic base portion (243I), a base link portion (243L), and a base contact portion (245C). The intrinsic base portion is situated below the emitter and above material of the collector. The base link portion extends between the intrinsic base portion and the base contact portions. The spacing structure includes an isolating dielectric layer (267-1 or 267-2) and a spacing component. The dielectric layer extends along the upper semiconductor surface. The spacing component includes a lateral spacing portion (269-1 or 269-2) of largely non-monocrystalline semiconductor material, preferably polycrystalline semiconductor material, situated on the dielectric layer above the base link portion.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: November 6, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Jeng-Jiun Yang, Constantin Bulucea
  • Patent number: 8305677
    Abstract: A system and method for operating an electronic device used in light processing. A method comprises altering a spatial relationship between a spatial light modulator (SLM) and a light incident on the SLM, shifting light modulator states of a first portion of light modulators to a second portion of light modulators, and placing a third portion of light modulators in the SLM into a performance degradation-reducing mode. The amount of shifting performed is proportional to the amount of change in the spatial relationship. The method allows for a change in light modulators used to modulate the light, thereby preventing the overuse of some of the light modulators, which may help to prevent degradation of the light modulators. The performance degradation reducing mode may help to further reduce or even reverse the performance degradation of the light modulators.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Terry Alan Bartlett, James Anthony Strain, Paul L. Rancuret