Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation is regions are formed over a semiconductive substrate.

Abstract: The invention includes a method for forming graded junction regions comprising: a) providing a semiconductor material wafer; b) providing a transistor gate over the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) providing sidewall spacers adjacent the sidewalls of the transistor gate, the sidewall spacers having a lateral thickness; d) decreasing the lateral thickness of the sidewall spacers; and e) after decreasing the lateral thickness of the sidewall spacers, implanting a conductivity-enhancing dopant into the semiconductor material to form graded junction regions operatively adjacent the transistor gate.

Abstract: In one aspect, the invention includes a method of etching, comprising: a) forming a material over a substrate, the material comprising a lower portion near the substrate and an upper portion above the lower portion; b) providing a quantity of detectable atoms within the material, the detectable atoms being provided at a different concentration in the lower portion than in the upper portion; c) etching into the material and forming etching debris; and d) detecting the detectable atoms in the debris. In another aspect, the invention includes a method of etching, comprising: a) providing a semiconductor wafer substrate, the substrate having a center and an edge; b) forming a material over the substrate, the material comprising detectable atoms; c) etching into the material and forming etching debris; d) detecting the detectable atoms in the debris; and e) estimating a degree of center-to-edge uniformity of the etching from the detecting.

Abstract: A method of manufacturing and testing an electronic circuit, the method comprising forming a plurality of conductive traces on a substrate and providing a gap in one of the conductive traces; attaching a circuit component to the substrate and coupling the circuit component to at least one of the conductive traces; supporting a battery on the substrate, and coupling the battery to at least one of the conductive traces, wherein a completed circuit would be defined, including the traces, circuit component, and battery, but for the gap; verifying electrical connections by performing an in circuit test, after the circuit component is attached and the battery is supported; and employing a jumper to electrically close the gap, and complete the circuit, after verifying electrical connections.

Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.

Abstract: In one aspect, the invention encompasses a semiconductor processing method comprising contacting a surface with a liquid solution comprising at least one fluorine-containing species and a temperature of at least about 40° C. In another aspect, the invention encompasses a method of passivating a silicon-comprising layer comprising contacting the layer with a liquid solution comprising hydrogen fluoride and a temperature of at least about 40° C. In yet another aspect, the invention encompasses a method of forming hemispherical grain polysilicon comprising: a) forming a layer comprising substantially amorphous silicon over a substrate; b) contacting the layer comprising substantially amorphous silicon with a liquid solution comprising fluorine-containing species and a temperature of at least about 40° C.; c) seeding the layer comprising substantially amorphous silicon; and d) annealing the seeded layer to convert at least a portion of the seeded layer to hemispherical grain polysilicon.

Abstract: A communications system including a radio frequency identification device including an integrated circuit having a single die including a microprocessor, a receiver coupled to the microprocessor, and a backscatter transmitter coupled to the microprocessor, the integrated circuit having a digital output, and the receiver being configured to receive wireless communications from a remote interrogator; and a digital to analog converter external of the single die and having a digital input coupled to the digital output of the integrated circuit, and having an analog output configured to be coupled to an analog device. A communications method including coupling a digital to analog converter to a radio frequency identification device.

Abstract: In one aspect, the invention includes a method of forming a material comprising tungsten and nitrogen, comprising: a) providing a substrate; b) depositing a layer comprising tungsten and nitrogen over the substrate; and c) in a separate step from the depositing, exposing the layer comprising tungsten and nitrogen to a nitrogen-containing plasma. In another aspect, the invention includes a method of forming a capacitor, comprising: a) forming a first electrical node; b) forming a dielectric layer over the first electrical node; c) forming a second electrical node; and d) providing a layer comprising tungsten and nitrogen between the dielectric layer and one of the electrical nodes, the providing comprising; i) depositing a layer comprising tungsten and nitrogen; and ii) in a separate step from the depositing, exposing the layer comprising tungsten and nitrogen to a nitrogen-containing plasma.

Abstract: An expandable stinger planter is described which includes a base frame and a pivot frame mounted to the base frame for pivotal movement thereon about multiple pivot axes. A stinger comprised of a pair of elongated probes is mounted to the pivot frame and extending to bottom ends. A stinger mounting frame is operatively positioned between the pivot frame and at least one of the elongated probes. An actuator on the stinger mounting frame is operable to shift the bottom ends between a closed position and an open wherein the bottom ends are opened and form a plant discharge opening. An internal plant receiving receptacle within the probes is open to the plant discharge opening at the open position whereby a plant placed in the plant receiving receptacle may be discharged through the plant discharge opening.

Abstract: An extended symbol Galois field error correcting device is provided. The device includes a singly-extended Reed-Solomon encoder configured to generate an encoded codeword, {tilde over (c)}(x). The device also includes a channel medium that is signal coupled with the singly-extended Reed-Solomon encoder. The channel medium is configured to receive the encoded codeword, {tilde over (c)}(x), and output a received input codeword, {tilde over (r)}(x). The channel medium is capable of introducing error, {tilde over (e)}(x), to the encoded codeword, {tilde over (c)}(x). The device further includes a singly-extended Reed-Solomon decoder that is coupled with the channel medium. The singly-extended Reed-Solomon decoder is configured to receive the received input codeword, {tilde over (r)}(x). The singly-extended Reed-Solomon decoder has error detection circuitry and extended symbol correction circuitry.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: An image processing system including a display output processor using Temporal Gamma Processing (TGP) and Reverse Super-resolution (RSR) techniques to process images. TGP assures that the time-related representation of an image is as accurate as possible, and thus, based on a previous frame value and a known transfer function of the display modulation system, adjusts its output values to provide a desired output value during display of a desired frame. RSR performs a superset of the frame rate conversion process for converting between disparate input and output frame rates. RSR, improving display quality when intended display images have apparent resolution higher than can be supported by an image modulator, sequences lower resolution images at higher frame rates to simulate higher resolution outputs.

Abstract: A method of forming a circuitry isolation region within a semiconductive wafer comprises defining active area and isolation area over a semiconductive wafer. Semiconductive wafer material within the isolation area is wet etched using an etch chemistry which forms an isolation trench proximate the active area region having lowestmost corners within the trench which are rounded. Electrically insulating material is formed within the trench over the previously formed round corners. In accordance with another aspect, the semiconductive wafer material within the isolation area is etched using an etch chemistry which is substantially selective relative to semiconductive wafer material within the active area to form an isolation trench proximate the active area region. In accordance with still another aspect, a method of forming a circuitry isolation region within a semiconductive wafer comprises masking an active area region over a semiconductive wafer.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: A siding mounted light clip is described for releasable attachment to a lap type siding member. The clip includes a clip body with a light mount part and a siding mount part. The siding mount part includes a base member with a flange configured to slide under a lap type siding member. A leg member extends from the base member to the light mount part. A resilient clamp member is mounted to the leg member and forms an expandable siding receiving recess with the flange. A lap type siding member may be releasably gripped within the expandable siding receiving recess between the flange and resilient clamp member.

Abstract: In one aspect the invention includes a method of protecting aluminum within an aluminum-comprising layer from electrochemical degradation during semiconductor processing comprising, providing a material within the layer having a lower reduction potential than aluminum. In another aspect, the invention includes a semiconductor processing method of forming and processing an aluminum-comprising mass, comprising: a) forming the aluminum-comprising layer mass to comprise a material having a lower reduction potential than aluminum; and b) exposing the aluminum-comprising mass to an electrolytic substance, the material protecting aluminum within the aluminum-comprising layer from electrochemical degradation during the exposing. In yet another aspect, the invention includes an aluminum-comprising layer over or within a semiconductor wafer substrate and comprising a material having a lower reduction potential than aluminum.

Abstract: In one implementation, A method of forming semiconductive material active area having a proximity gettering region received therein includes providing a substrate comprising bulk semiconductive material. A proximity gettering region is formed within the bulk semiconductive material within a desired active area by ion implanting at least one impurity into the bulk semiconductive material. After forming the proximity gettering region, thickness of the bulk semiconductive material is increased in a blanket manner at least within the desired active area. In one implementation, a method of processing a monocrystalline silicon substrate includes forming a proximity gettering region within monocrystalline silicon of a monocrystalline silicon substrate. After forming the proximity gettering region, epitaxial monocrystalline silicon is formed on the substrate monocrystalline silicon to blanketly increase its thickness at least over the proximity gettering region.

Abstract: Electronic communication devices, methods of forming electrical communication devices, and communications methods are provided. An electronic communication device adapted to receive electronic signals includes: a housing having a substrate and an encapsulant; an integrated circuit provided within the housing and having comprising transponder circuitry operable to communicate an identification signal responsive to receiving a polling signal; an antenna provided within the housing and being coupled with the transponder circuitry; and a ground plane provided within the housing and being spaced from the antenna and configured to shield some of the electronic signals from the antenna and reflect others of the electronic signals towards the antenna.

Abstract: A new and distinctive variety of peach tree denominated varietally as Burpeachfour and which is characterized as to novelty by a date of maturity for commercial harvesting and shipment of approximately August 28 to September 8 under the ecological conditions prevailing in the San Joaquin Valley of central California.