Abstract: Methods of forming face plate assemblies are described. In one implementation, a substrate is patterned with photoresist and a first phosphor-comprising material is formed over first surface areas of the substrate. The photoresist is stripped leaving some of the first phosphor-comprising material over substrate areas other than the first areas. Photoresist is again formed over the substrate and processed to expose second substrate areas which are different from the first substrate areas. In a preferred aspect, processing the photoresist comprises using a heated aqueous developing solution comprising an acid, e.g. lactic acid, effective to dislodge and remove first phosphor-comprising material from beneath the developed photoresist. A second phosphor-comprising material is formed over the substrate and the exposed second areas, with trace deposits being left over other substrate areas.

Abstract: Methods of forming dielectric layers and methods of forming capacitors are described. In one embodiment, a substrate is placed within a chemical vapor deposition reactor. In the presence of activated fluorine, a dielectric layer is chemical vapor deposited over the substrate and comprises fluorine from the activated fluorine. In another embodiment, a fluorine-comprising material is formed over at least a portion of an internal surface of the reactor. Subsequently, a dielectric layer is chemical vapor deposited over the substrate. During deposition, at least some of the fluorine-comprising material is dislodged from the surface portion and incorporated in the dielectric layer. In another embodiment, the internal surface of the reactor is treated with a gas plasma generated from a source gas comprising fluorine, sufficient to leave some residual fluorine thereover.

Abstract: A thin film transistor includes, a) a thin film source region; b) a thin film drain region; c) a polycrystalline thin film channel region intermediate the thin film source region and the thin film drain region; d) a transistor gate and gate dielectric operatively positioned adjacent the thin film channel region; and e) the thin film channel region comprising at least an inner layer, an outer layer and a middle layer sandwiched between the inner layer and the outer layer, the inner layer and the outer layer comprising polycrystalline silicon and having respective energy bandgaps, the middle sandwich layer comprising a polycrystalline material and having a lower energy bandgap than either of the inner and outer layers. Alternately, the channel region is homogeneous, comprising germanium or an alloy of polycrystalline silicon and germanium.

Abstract: Semiconductor processing methods of forming integrated circuitry, and in particular, methods of forming such circuitry utilizing dual damascene technology, and resultant integrated circuitry constructions are described. In one embodiment, a substrate is provided having a circuit device. At least three layers are formed over the substrate and through which electrical connection is to be made with the circuit device. The three layers comprise first and second layers having an etch stop layer interposed therebetween. A contact opening is formed through the three layers and a patterned masking layer is formed over the three layers to define a conductive line pattern. Material of an uppermost of the first and second layers is selectively removed relative to the etch stop layer and defines a trough joined with the contact opening. Conductive material is subsequently formed within the trough and contact opening.

Abstract: In one aspect, the invention encompasses a method of utilizing a vaporization surface as an electrode to form a plasma within a vapor forming device. In another aspect, the invention encompasses a method of chemical vapor deposition. A vaporization surface is provided and heated. At least one material is flowed past the heated surface to vaporize the material. A deposit forms on the vaporization surface during the vaporization. The vaporization surface is then utilized as an electrode to form a plasma, and at least a portion of the deposit is removed with the plasma.

Abstract: The invention includes a semiconductor wafer assembly, comprising: a) a semiconductor wafer substrate; and b) alternating first and second layers over the semiconductor wafer substrate, the alternating layers comprising at least one first layer and at least one second layer, the first layer comprising a first material and the second layer comprising a second material, the second material comprising atoms selected from the group consisting of yttrium, lanthanides, actinides, calcium, magnesium and mixtures thereof.

Abstract: The invention includes a method for forming graded junction regions comprising: a) providing a semiconductor material wafer; b) providing a transistor gate over the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) providing sidewall spacers adjacent the sidewalls of the transistor gate, the sidewall spacers having a lateral thickness; d) decreasing the lateral thickness of the sidewall spacers; and e) after decreasing the lateral thickness of the sidewall spacers, implanting a conductivity-enhancing dopant into the semiconductor material to form graded junction regions operatively adjacent the transistor gate.

Abstract: In one aspect, the invention encompasses a semiconductor processing method of forming a metal-comprising layer over a substrate. A substrate is provided within a reaction chamber, and a source of a metal-comprising precursor is provided external to the reaction chamber. The metal-comprising precursor comprises a metal coordinated with at least one Lewis base to form a complex having a stoichiometric ratio of the at least one Lewis base to the metal. An amount of the at least one Lewis base is distributed within the source to an amount that is in excess of the stoichiometric ratio. At least some of the metal-comprising precursor is transported from the source to the reaction chamber. A metal is deposited from the metal-comprising precursor and onto the substrate within the reaction chamber. In another aspect, the invention encompasses a method of storing a metal-comprising material. A metal-comprising material is dispersed within a solution.

Abstract: Semiconductor capacitor constructions, DRAM cell constructions, methods of forming semiconductor capacitor constructions, methods of forming DRAM cell constructions, and integrated circuits incorporating capacitor structures and DRAM cell structures are encompassed by the invention. The invention includes a method comprising: a) forming an opening within an insulative layer and over a node location; b) forming a spacer within the opening to narrow the opening, the spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed opening; c) removing a portion of the insulative layer from proximate the outer surface to expose at least a portion of the outer surface; d) forming a storage node layer in electrical connection with the node location, extending along the spacer inner surface, and extending along the exposed spacer outer surface; and e) forming a dielectric layer and a cell plate layer operatively proximate the storage node layer.

Abstract: A grapple positioning device is described for attachment to a grapple and boom, wherein the grapple is pivotably mounted to an end of the boom. The device includes an extensible ram mountable to the boom and extending to a pusher plate. A follower is mountable to the grapple, and the ram is operable to extend and move the pusher plate against the follower and thereby pivot the grapple away from the boom. The ram is also operable to retract to move the pusher plate in a direction toward the boom and away from the follower.

Abstract: A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure chemical vapor deposition at a pressure of at least 1 Torr, a temperature of less than 700° C. and using feed gases comprising a silicon hydride and ammonia. The substrate with silicon nitride layer is exposed to oxidizing conditions comprising at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride over the doped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed over the silicon dioxide layer and the first electrode. In another implementation, a layer comprising undoped oxide is formed over a doped oxide layer.

Abstract: A radio frequency identification device comprises an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receiver, the transmitter, and the microprocessor. Because the device includes an active transponder, instead of a transponder which relies on magnetic coupling for power, the device has a much greater range.

Abstract: A ram cylinder piston stroke stop is disclosed, including a pair of opposed piston shaft gripping members each formed in an extruded shape along an axis with an integral extruded axially open spring end receiving socket. A spring includes opposed ends that are engaged within the spring end receiving sockets.

Abstract: Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically shaped devices relative to the patterned device outlines. Individual formed devices are spaced from at least one other of the devices by a distance no more than a width of one of the electrically insulative spacers. In such manner, device pitch is reduced by almost fifty percent. According to one aspect, elongated electrically conductive lines are formed. According to another aspect, capacitors are formed which, according to a preferred embodiment form part of a dynamic random access memory (DRAM) array.

Abstract: The invention includes a method of increasing polymerization within a condensation polymer. A substantially dry condensation polymer material is provided. The material is exposed to radiation having a frequency less than microwave frequency for a time of at least about 0.5 hour to increase an amount of polymerization within the material. The invention also includes a method of treating a polyamide material. A polymeric polyamide material is provided and exposed to first radiation having a first power intensity. The material is then exposed to second radiation having a second power intensity. The first power intensity is higher than the second power intensity. Additionally, the invention includes an apparatus. The apparatus includes an inlet port through which a feed material enters the apparatus, and an outlet port through which the feed material passes out of the apparatus.

Abstract: In one aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) enriching a portion of the thickness of the silicon nitride layer with silicon, the portion comprising less than or equal to about 95% of the thickness of the layer of silicon nitride. In another aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) increasing a refractive index of a first portion of the thickness of the silicon nitride layer relative to a refractive index of a second portion of the silicon nitride layer, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer.