Abstract: A method of forming a conductive connection between a first region and a second region includes forming a first titanium comprising layer over and in electrical connection with the first region. The first layer is exposed to a nitrogen containing plasma effective to transform at least an outer portion thereof into a second layer comprising titanium nitride. An elemental titanium comprising third layer is formed over the second layer. The third layer is exposed to a nitrogen containing plasma effective to transform at least an outer portion thereof into a layer comprising titanium nitride. The second region is formed over and in electrical connection with the transformed third layer. A method of forming a conductive line includes a conductively doped silicon comprising semiconductive material being formed. Titanium is deposited over the semiconductive material to form a first layer in electrical connection with the semiconductive material.

Abstract: Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material. In another embodiment, a capacitor storage node is formed having an uppermost surface and a side surface joined therewith. A protective cap is formed over the uppe-most surface and a capacitor dielectric layer is formed over the side surface and protective cap. A cell electrode layer is formed over the side surface of the capacitor storage node.

Abstract: The invention encompasses an electrical apparatus. Such apparatus comprises a first substrate having first circuitry supported thereby. The first circuitry defines at least a portion of a radio frequency identification device. At least one first electrical node is supported by the substrate and in electrical connection with the first circuitry. The apparatus further comprises an input device comprising a second substrate and second circuitry on the second substrate. The second circuitry is in electrical communication with at least one second electrical node. Neither of the first nor second electrical nodes is a lead, and the second electrical node is adhered to the first electrical node to electrically connect the input device with the radio frequency identification device. The invention also encompasses a termite-sensing apparatus. Additionally, the invention encompasses methods of forming electrical apparatuses, and methods for sensing termites.

Abstract: A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; f) after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; g) filling the contact opening to the node location with electrically conductive material; h) rendering the sidewall spacer electrically conductive; and i) etching the electrically conductive material to form an electrically conducti

Abstract: Methods of forming integrated circuitry lines such as coaxial integrated circuitry interconnect lines, and related integrated circuitry are described. An inner conductive coaxial line component is formed which extends through a substrate. An outer conductive coaxial line component and coaxial dielectric material are formed, with the coaxial dielectric material being formed operably proximate and between the inner and outer conductive coaxial line components. In a preferred implementation, the substrate includes front and back surfaces, and a hole is formed which extends through the substrate and between the front and back surfaces. In one implementation, the outer conductive coaxial line component constitutes doped semiconductive material. In another implementation, such constitutes a layer of metal-comprising material. A layer of dielectric material is formed over and radially inwardly of the outer line component. Conductive material is then formed over and radially inwardly of the dielectric material layer.

Abstract: The invention comprises capacitors and methods of forming capacitors. In one implementation, a method of forming a capacitor includes forming a first capacitor electrode. An Si3N4 comprising capacitor dielectric layer is formed over the first capacitor electrode. The Si3N4 comprising layer is oxidized in the presence of a chlorine containing atmosphere under conditions which form a silicon oxynitride layer comprising chlorine atop the Si3N4 layer. In one aspect, the oxidizing sequentially comprises a dry oxidation in the presence of an oxygen containing gas in the substantial absence of chlorine, a dry oxidation in the presence of a gas comprising oxygen and chlorine, and a wet oxidation comprising chlorine. A second capacitor electrode is formed over the chlorine containing silicon oxynitride layer. In one implementation, a method of forming a capacitor comprises forming a first capacitor electrode.

Abstract: A radio frequency identification device comprises an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receiver, the transmitter, and the microprocessor. Because the device includes an active transponder, instead of a transponder which relies on magnetic coupling for power, the device has a much greater range.

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components.

Abstract: The invention includes colorless compounds having a central core and at least two arms extending from the core. The core can comprise one or more atoms. The at least two arms have the formula In such formula, Z is a segment of one or more atoms; j is an integer from 1 to about 300 and can be different at one of the at least two arms than at another of the at least two arms; Q is an alkyl or aryl group and can vary amongst different alkyl and aryl groups within the colorless compound; and n is an integer greater than 1 and can be different at one of the at least two arms than at another of the at least two arms. In other aspects, the invention encompasses phase change inks incorporating the above-described colorless compound as toughening agent, and methods of printing with such phase change inks.

Abstract: A deep tensiometer is configured with an outer guide tube having a vented interval along a perforate section at its lower end, which is isolated from atmospheric pressure at or above grade. A transducer having a monitoring port and a reference port is located within a coaxial inner guide tube. The reference port of the transducer is open to the vented interval of the outer guide tube, which has the same gas pressure as in the sediment surrounding the tensiometer. The reference side of the pressure transducer is thus isolated from the effects of atmospheric pressure changes and relative to pressure changes in the material surrounding the tensiometer measurement location and so it is automatically compensated for such pressure changes.

Abstract: Conveying apparatuses, indication assemblies, methods of indicating operation of a conveying apparatus, and methods of operating a conveying apparatus are provided. According to one aspect, a conveying apparatus includes a frame; a bed configured to convey material in a direction; a drive device configured to impart movement to the bed; and an indication assembly configured to indicate operation of the conveying apparatus in an operational state. Another aspect provides a method of indicating operation of a conveying apparatus comprising: providing a conveying apparatus including a bed; supporting the bed using a frame; imparting movement to the bed to induce movement of material within the bed; and indicating operation of the conveying apparatus in an operational state.

Abstract: Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a, portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug.

Abstract: This invention includes a method and an apparatus for producing high purity titanium and high purity titanium so produced. The high purity titanium comprises titanium and less than 0.1 ppm, by weight, total of sodium, potassium, aluminum, iron, chromium, zirconium, vanadium and nickel.

Abstract: A liquid stabilizing baffle system is described in which a plurality of elongated strips are provided, each being formed of a flexible spring material. Each strip includes longitudinal side edges joining opposed ends. At least one end hole is formed in each strip inwardly adjacent each end, and each strip is foldable into a loop configuration with ends overlapping. Fastener members are provided to be received through aligned end holes of the strips. A connector is provided on each strip, configured to enable a plurality of the strips to be linked in succession with the strips folded into loop configurations to form a strand. In a preferred form the connector includes a set of geometric shaped holes formed through the strips in the loops, and a similarly shaped bar threaded through the holes to prevent relative rotation of the loops relative to one another.

Abstract: The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon.

Abstract: Methods of forming field effect transistors.

Abstract: Methods of forming flip chip bumps and related flip chip bump constructions are described. In one implementation, a bump of conductive material is formed over a substrate. At least a portion of the bump is dipped into a volume of conductive flowable material, with some of the flowable material remaining over the bump. The remaining flowable material over the bump is solidified and includes an outermost surface the entirety of which is outwardly exposed. In another implementation, the outermost surface include an uppermost generally planar surface away from the substrate. The solidified flowable material together with the conductive material of the bump provide a bump assembly having a height which is greater than the height of the original bump. The increased height is achieved without meaningfully increasing a width dimension of the bump proximate the substrate.

Abstract: A decorative submersible sculpture is described in which a submersible hollow body is formed with a peripheral wall structure. The wall structure defines an internal receptacle of a prescribed decorative shape that is configured to be filled by a visually opaque particulate medium and formed by the internal receptacle into the prescribed decorative shape. At least part of the wall structure is transparent and configured in such a manner that when the receptacle is filled with visually opaque particulate medium, the medium takes the form of the prescribed decorative shape and is visible through the transparent part or parts of the wall structure. The decorative shape will visually appear to be in a solid, self-supporting state, and the transparent parts of the wall structure will be substantially invisible.

Abstract: A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design. The automatic test pattern generation (ATPG) algorithm is operative to design and test an integrated circuit design.