Patents Represented by Attorney, Agent or Law Firm Wells, St. John, Roberts, Gregory & Matkin, P.S.
  • Patent number: 6344792
    Abstract: A method of manufacturing and testing an electronic circuit, the method comprising forming a plurality of conductive traces on a substrate and providing a gap in one of the conductive traces; attaching a circuit component to the substrate and coupling the circuit component to at least one of the conductive traces; supporting a battery on the substrate, and coupling the battery to at least one of the conductive traces, wherein a completed circuit would be defined, including the traces, circuit component, and battery, but for the gap; verifying electrical connections by performing an in circuit test, after the circuit component is attached and the battery is supported; and employing a jumper to electrically close the gap, and complete the circuit, after verifying electrical connections.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: February 5, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Mark E. Tuttle, Rickie C. Lake, Curtis M. Medlen
  • Patent number: 6344376
    Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: February 5, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Shubneesh Batra, Pierre C. Fazan
  • Patent number: 6342843
    Abstract: A communications system including a radio frequency identification device including an integrated circuit having a single die including a microprocessor, a receiver coupled to the microprocessor, and a backscatter transmitter coupled to the microprocessor, the integrated circuit having a digital output, and the receiver being configured to receive wireless communications from a remote interrogator; and a digital to analog converter external of the single die and having a digital input coupled to the digital output of the integrated circuit, and having an analog output configured to be coupled to an analog device. A communications method including coupling a digital to analog converter to a radio frequency identification device.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: January 29, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Scott Hahn, Mark T. Van Horn
  • Patent number: 6342417
    Abstract: In one aspect, the invention includes a method of forming a material comprising tungsten and nitrogen, comprising: a) providing a substrate; b) depositing a layer comprising tungsten and nitrogen over the substrate; and c) in a separate step from the depositing, exposing the layer comprising tungsten and nitrogen to a nitrogen-containing plasma. In another aspect, the invention includes a method of forming a capacitor, comprising: a) forming a first electrical node; b) forming a dielectric layer over the first electrical node; c) forming a second electrical node; and d) providing a layer comprising tungsten and nitrogen between the dielectric layer and one of the electrical nodes, the providing comprising; i) depositing a layer comprising tungsten and nitrogen; and ii) in a separate step from the depositing, exposing the layer comprising tungsten and nitrogen to a nitrogen-containing plasma.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: January 29, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Vishnu K. Agarwal, Gurtej S. Sandhu
  • Patent number: 6341362
    Abstract: An extended symbol Galois field error correcting device is provided. The device includes a singly-extended Reed-Solomon encoder configured to generate an encoded codeword, {tilde over (c)}(x). The device also includes a channel medium that is signal coupled with the singly-extended Reed-Solomon encoder. The channel medium is configured to receive the encoded codeword, {tilde over (c)}(x), and output a received input codeword, {tilde over (r)}(x). The channel medium is capable of introducing error, {tilde over (e)}(x), to the encoded codeword, {tilde over (c)}(x). The device further includes a singly-extended Reed-Solomon decoder that is coupled with the channel medium. The singly-extended Reed-Solomon decoder is configured to receive the received input codeword, {tilde over (r)}(x). The singly-extended Reed-Solomon decoder has error detection circuitry and extended symbol correction circuitry.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: January 22, 2002
    Assignee: VLSI Technology, Inc.
    Inventor: Habibollah Golnabi
  • Patent number: 6340624
    Abstract: A method of forming a circuitry isolation region within a semiconductive wafer comprises defining active area and isolation area over a semiconductive wafer. Semiconductive wafer material within the isolation area is wet etched using an etch chemistry which forms an isolation trench proximate the active area region having lowestmost corners within the trench which are rounded. Electrically insulating material is formed within the trench over the previously formed round corners. In accordance with another aspect, the semiconductive wafer material within the isolation area is etched using an etch chemistry which is substantially selective relative to semiconductive wafer material within the active area to form an isolation trench proximate the active area region. In accordance with still another aspect, a method of forming a circuitry isolation region within a semiconductive wafer comprises masking an active area region over a semiconductive wafer.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: January 22, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Trung Tri Doan, Mark Durcan
  • Patent number: 6340834
    Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: January 22, 2002
    Assignee: Micron Technology, Inc.
    Inventors: J. Brett Rolfson, Monte Manning
  • Patent number: 6340835
    Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: January 22, 2002
    Assignee: Micron Technology, Inc.
    Inventors: J. Brett Rolfson, Monte Manning
  • Patent number: 6338938
    Abstract: In one aspect the invention includes a method of forming a semiconductor device, comprising: a) forming a layer over a substrate; b) forming a plurality of openings extending into the layer; c) depositing particles on the layer; d) collecting the particles within the openings; and e) using the collected particles as a mask during etching of the underlying substrate to define features of the semiconductor device. In another aspect, the invention includes a method of forming a field emission display, comprising: a) forming a silicon dioxide layer over a conductive substrate; b) forming a plurality of openings extending into the silicon dioxide layer; c) depositing particles on the silicon dioxide layer; d) collecting the particles within the openings; e) while using the collected particles as a mask, etching the conductive substrate to form a plurality of conically shaped emitters from the conductive substrate; and f) forming a display screen spaced from said emitters.
    Type: Grant
    Filed: January 25, 2000
    Date of Patent: January 15, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Eric A. Lahaug
  • Patent number: 6338460
    Abstract: A siding mounted light clip is described for releasable attachment to a lap type siding member. The clip includes a clip body with a light mount part and a siding mount part. The siding mount part includes a base member with a flange configured to slide under a lap type siding member. A leg member extends from the base member to the light mount part. A resilient clamp member is mounted to the leg member and forms an expandable siding receiving recess with the flange. A lap type siding member may be releasably gripped within the expandable siding receiving recess between the flange and resilient clamp member.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: January 15, 2002
    Inventor: Donald D. Rumpel
  • Patent number: 6339026
    Abstract: In one aspect the invention includes a method of protecting aluminum within an aluminum-comprising layer from electrochemical degradation during semiconductor processing comprising, providing a material within the layer having a lower reduction potential than aluminum. In another aspect, the invention includes a semiconductor processing method of forming and processing an aluminum-comprising mass, comprising: a) forming the aluminum-comprising layer mass to comprise a material having a lower reduction potential than aluminum; and b) exposing the aluminum-comprising mass to an electrolytic substance, the material protecting aluminum within the aluminum-comprising layer from electrochemical degradation during the exposing. In yet another aspect, the invention includes an aluminum-comprising layer over or within a semiconductor wafer substrate and comprising a material having a lower reduction potential than aluminum.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: January 15, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Allen McTeer
  • Patent number: 6339011
    Abstract: In one implementation, A method of forming semiconductive material active area having a proximity gettering region received therein includes providing a substrate comprising bulk semiconductive material. A proximity gettering region is formed within the bulk semiconductive material within a desired active area by ion implanting at least one impurity into the bulk semiconductive material. After forming the proximity gettering region, thickness of the bulk semiconductive material is increased in a blanket manner at least within the desired active area. In one implementation, a method of processing a monocrystalline silicon substrate includes forming a proximity gettering region within monocrystalline silicon of a monocrystalline silicon substrate. After forming the proximity gettering region, epitaxial monocrystalline silicon is formed on the substrate monocrystalline silicon to blanketly increase its thickness at least over the proximity gettering region.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: January 15, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Sergei Koveshnikov
  • Patent number: 6336477
    Abstract: In a weaving device, a weaving device frame mounts a plurality of eyelets. A frame module, releasably borne by the weaving device frame is readily detachable from and controls movement of the respective eyelets. The frame module forms a readily removable component of the weaving device.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: January 8, 2002
    Assignee: WIS Seaming
    Inventors: Chester F. Kutzleb, Roger King, Anders Bostrom, Robert Kellogg
  • Patent number: 6337274
    Abstract: The invention includes buried bit line memory circuitry, methods of forming buried bit line memory circuitry, and semiconductor processing methods of forming conductive lines. In but one implementation, a semiconductor processing method of forming a conductive line includes forming a silicon comprising region over a substrate. A TiNx comprising layer is deposited over the silicon comprising region, where “x” is greater than 0 and less than 1. The TiNx comprising layer is annealed in a nitrogen containing atmosphere effective to transform at least an outermost portion of the TiNx layer over the silicon comprising region to TiN. After the annealing, an elemental tungsten comprising layer is deposited on the TiN and at least the elemental tungsten comprising layer, the TiN, and any remaining TiNx layer is patterned into conductive line. In one implementation, a method such as the above is utilized in the fabrication of buried bit line memory circuitry.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: January 8, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, Pai-Hung Pan, Scott Jeffrey DeBoer
  • Patent number: 6337634
    Abstract: A radio frequency identification device comprises an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receiver, the transmitter, and the microprocessor. Because the device includes an active transponder, instead of a transponder which relies on magnetic coupling for power, the device has a much greater range.
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: January 8, 2002
    Assignee: Micron Technology, Inc.
    Inventors: James E. O'Toole, John R. Tuttle, Mark E. Tuttle, Tyler Lowrey, Kevin M. Devereaux, George E. Pax, Brian P. Higgins, David K. Ovard, Shu-Sun Yu, Robert R. Rotzoll
  • Patent number: 6337243
    Abstract: A semiconductor processing method of providing a hemispherical grain polysilicon layer atop a substrate includes, a) providing a substantially amorphous layer of silicon over a substrate at a selected temperature; b) raising the temperature of the substantially amorphous silicon layer to a higher dielectric layer deposition temperature, the temperature raising being effective to transform the amorphous silicon layer into hemispherical grain polysilicon; and c) depositing a dielectric layer over the silicon layer at the higher dielectric deposition temperature. Transformation to hemispherical grain might occur during the temperature rise to the higher dielectric layer deposition temperature, after the higher dielectric layer deposition temperature has been achieved but before dielectric layer deposition, or after the higher dielectric layer deposition temperature has been achieved and during dielectric layer deposition.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: January 8, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Er-Xang Ping, Randhir P. S. Thakur
  • Patent number: 6337237
    Abstract: A capacitor processing method includes forming a capacitor comprising first and second electrodes having a capacitor dielectric region therebetween. The first electrode interfaces with the capacitor dielectric region at a first interface. The second electrode interfaces with the capacitor dielectric region at a second interface. The capacitor dielectric region has a plurality of oxygen vacancies therein. After forming the capacitor, an electric field is applied to the capacitor dielectric region to cause oxygen vacancies to migrate towards one of the first and second interfaces. Oxygen atoms are preferably provided at the one interface effective to fill at least a portion of the oxygen vacancies in the capacitor dielectric region. Preferably at least a portion of the oxygen vacancies in the high k capacitor dielectric region are filled from oxide material comprising the first or second electrode most proximate the one interface.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: January 8, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Gurtej S. Sandhu
  • Patent number: 6337261
    Abstract: Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line.
    Type: Grant
    Filed: October 11, 2000
    Date of Patent: January 8, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 6337244
    Abstract: A method of forming a line of FLASH memory cells includes forming a first line of floating gates over a crystalline silicon semiconductor substrate. An alternating series of SiO2 isolation regions and active areas are provided in the semiconductor substrate in a second line adjacent and along at least a portion of the first line of floating gates. The series of active areas define discrete transistor source areas. A masking layer is formed over the floating gates, the regions and the areas. A third line mask opening is formed in the masking layer over at least a portion of the second line. Anisotropic etching is conducted of the SiO2 isolation regions exposed through the third line mask opening substantially selectively relative to crystalline silicon exposed through the third line mask opening using a gas chemistry comprising a combination of at least one non-hydrogen containing fluorocarbon having at least three carbon atoms and at least one hydrogen containing fluorocarbon.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: January 8, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Kirk D. Prall, Guy T. Blalock
  • Patent number: 6335254
    Abstract: In accordance with an aspect of the invention, a transistor is formed having a transistor gate, a gate dielectric layer and source/drain regions. The transistor gate includes at least two conductive layers of different conductive materials. One of the two conductive layers is more proximate the gate dielectric layer than the other of the two conductive layers. A source/drain reoxidation is conducted prior to forming the other conductive layer. In another aspect of the invention, a transistor has a transistor gate, a gate dielectric layer and source/drain regions. The transistor gate includes a tungsten layer. A source/drain reoxidation is conducted prior to forming the tungsten layer of the gate. In yet another aspect of the invention, a semiconductor processing method forms a transistor gate having insulative sidewall spacers thereover. After forming the insulative sidewall spacers, an outer conductive tungsten layer of the transistor gate is formed.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: January 1, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Jigish D. Trivedi