Abstract: The invention encompasses a device for sensing living organisms. Such device comprises a loop of conductive material extending over a substrate, and an insulative protective material over the loop of conductive material. The device further comprises a circuit which includes the conductive material as a first circuit component and which further includes a transponder as a second circuit component. The transponder is configured to emit a first signal if the loop of conductive material is continuous, and a second signal if the loop of conductive material is broken. The invention also encompasses a device for sensing termites. Such device comprises at least two wooden blocks separated by a gap, and a loop of conductive material within the gap. The device further comprises an insulative protective material over the loop of conductive material.

Abstract: The invention encompasses resistors comprising a thin layer of dielectric material and methods of forming such resistors. The invention also encompasses integrated circuitry comprising such resistors, including SRAM circuitry, and encompasses methods of forming such integrated circuitry. In one aspect, the invention includes a resistor construction for electrically connecting a first node location to a second node location comprising: a) a first conductive layer in electrical connection with the first node location; b) a second conductive layer in electrical connection with the second node location; and c) a dielectric material intermediate the first conductive layer and the second conductive layer and having a thickness of from about 15 Angstroms to about 60 Angstroms.

Abstract: A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; f) after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; g) filling the contact opening to the node location with electrically conductive material; h) rendering the sidewall spacer electrically conductive; and i) etching the electrically conductive material to form an electrically conducti

Abstract: In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer.

Abstract: Integrated circuitry fuse forming methods, integrated circuity programming methods, and related integrated circuitry are described. In one implementation, a first layer comprising a first conductive material is formed over a substrate. A second layer comprising a second conductive material different from the first conductive material is formed over the first layer and in conductive connection therewith. A fuse area is formed by removing at least a portion of one of the first and second layers. In a preferred aspect, an assembly of layers comprising one layer disposed intermediate two conductive layers is provided. At least a portion of the one layer is removed from between the two layers to provide a void therebetween. In another aspect, programming circuitry is provided over a substrate upon which the assembly of layers is provided.

Abstract: Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically shaped devices relative to the patterned device outlines. Individual formed devices are spaced from at least one other of the devices by a distance no more than a width of one of the electrically insulative spacers. In such manner, device pitch is reduced by almost fifty percent. According to one aspect, elongated electrically conductive lines are formed. According to another aspect, capacitors are formed which, according to a preferred embodiment form part of a dynamic random access memory (DRAM) array.

Abstract: In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer.

Abstract: In one aspect, the invention encompasses a method of manufacturing a stencil mask comprising: a) defining a plurality of opening locations within a substrate; b) providing a dopant within the substrate, the dopant being provided in a pattern to form a plurality of first regions doped to a concentration with a dopant and one or more second regions not doped to the concentration with the dopant, individual first regions surrounding individual opening locations; c) forming a plurality of openings within the opening locations, the individual openings extending into the substrate; and d) forming a stencil mask from the substrate having the openings extending therein.

Abstract: A method of defining at least two different field effect transistor channel lengths includes forming a channel defining layer over a substrate, the semiconductor substrate having a mean global outer surface extending along a plane. First and second openings are etched into the channel defining layer. The first and second openings respectively have a pair of opposing sidewalls having substantially straight linear segments which are angled from the plane. The straight linear segments of the opposing sidewalls of the first opening are angled differently from the plane than the straight linear segments of the opposing sidewalls of the second opening and are thereby of different lengths. Integrated circuitry includes a first field effect transistor and a second field effect transistor. The first and second field effect transistors have respective channel lengths defined along their gate dielectric layers and respectively have at least some portion which is substantially straight linear.

Abstract: A circuit probing method includes contacting a conductive probe with a contact pad of an electronic circuit. An electric signal is sent between the contacted probe and the contact pad. After sending the signal, the conductive probe and contact pad are removed from contacting one another. After the removing, the conductive probe is chemically cleaned. In a further aspect, an integrated circuit on a semiconductor substrate has at least one conductive contact pad. A circuit probe formed from a semiconductor wafer has at least one conductive projecting apex. The conductive apex is brought into contact with the contact pad. An electric signal is sent between the contacted contact pad and the projecting apex. After sending the signal, the apex and contact pad are removed from contacting one another. After the removing, the conductive apex of the circuit probe is chemically cleaned.

Abstract: An apparatus for semiconductor processing includes: a) at least one support member comprising an upper surface for supporting a semiconductor wafer; b) a component through which the support member extends, the component comprising a front surface and a back surface, at least one of the support member and the component being movable relative to the other of the support member and the component such that the support member can support a wafer in an elevated position above the front surface and can be withdrawn into the component to lower the wafer relative to the front surface of the component; and c) a block joined to the support member below the component back surface, the block engaging the component back surface when the support member upper surface extends above the component to a predetermined distance, the block preventing the support member upper surface from extending beyond the front surface by more than the predetermined distance.

Abstract: Conductive lines, such as co-axial lines, integrated circuitry incorporating such conductive lines, and methods of forming the same are described. In one aspect, a substrate having an outer surface is provided. A masking material is formed over the outer surface and subsequently patterned to form a conductive line pattern. An inner conductive layer is formed within the conductive line pattern, followed by formation of a dielectric layer thereover and an outer conductive layer over the dielectric layer. Preferred implementations include forming the inner conductive layer through electroplating, or alternatively, electroless plating techniques. Other preferred implementations include forming the dielectric layer from suitable polymer materials having desired dielectric properties. A vapor-deposited dielectric layer of Parylene is one such preferred dielectric material.

Abstract: Material is separately plasma deposited over a plurality of semiconductor substrates within a chamber of a plasma deposition tool. The substrates are received over a susceptor during the respective depositings. Intermediate at least some of the plasma depositings, a reactive chamber treating gas is provided within the chamber in a nonpiasma environment and with at least a majority of the susceptor being outwardly exposed. Intermediate at least some of the plasma depositings, internal chamber surfaces are at least partially cleaned in a plasma environment using a cleaning gas and with at least a majority of the susceptor being covered. A plasma deposition tool operating method sequentially includes first plasma depositing a material over a first semiconductor substrate received over a susceptor within a chamber of a plasma deposition tool. The first depositing results in a residue forming over at least some internal chamber surfaces. The first substrate is removed from the chamber.

Abstract: A method of jointly forming stacked capacitors and antifuses includes, a) providing a common layer of electrically conductive material to form both a capacitor storage node and an inner antifuse plate; b) providing a common layer of dielectric material over the capacitor storage node and the inner antifuse plate, the common layer of dielectric material comprising both an intervening capacitor dielectric element and an intervening antifuse dielectric element, the common layer of dielectric material having a first breakdown voltage per unit length value for a given current per unit area; c) providing a common layer of electrically conductive material over the common layer of dielectric material to form both a capacitor cell layer and an outer antifuse plate; d) providing a lateral edge of the outer antifuse plate and a lateral edge of the intervening antifuse dielectric element; and e) depositing an antifuse breakdown layer of dielectric material over the lateral edges of the outer antifuse plate and the interv

Abstract: Methods of forming contact openings and methods of controlling the degree of taper of contact openings are described. In one implementation, a layer is first etched through a contact mask opening using a first set of etching conditions. The etching conditions provide a first degree of sidewall taper from vertical, if etching completely through the layer. After the first etching, the layer is second etched through the contact mask opening using a second set of etching conditions. The second set of etching conditions provide a second degree of sidewall taper from vertical, if etching completely through the layer. The second degree of sidewall taper is different from the first degree of taper. In another embodiment, a material through which a contact opening is to be etched to a selected depth is formed over a substrate. A masking layer having an opening therein is formed over the material.

Abstract: An ice sculpture mold, forming assembly and process is described in which a mold body is releasably received within an immersion tank having an open top end defined by a peripheral rim, and a closed bottom. The mold includes an internal cavity shaped as a negative of a selected ice sculpture form, and includes a top section positionable adjacent the open top end of the immersion tank and a bottom section positionable adjacent the closed bottom of the immersion tank. The mold body also includes at least one water intake and discharge openings formed in the upper section mold body, openly communicating with the internal cavity. A water circulating pump and water delivery tube are connected to each intake opening. The water discharge and intake openings are positioned on the mold to enable circulation of water within the assembled mold cavity to facilitate freezing of water in the assembled mold cavity to form an ice sculpture that is visually clear and devoid of clouding and air bubbles.

Abstract: Semiconductor processors, sensors, semiconductor processing systems, semiconductor workpiece processing methods, and turbidity monitoring methods are provided. According to one aspect, a semiconductor processor includes a process chamber configured to receive a semiconductor workpiece for processing; a supply connection in fluid communication with the process chamber and configured to supply slurry to the process chamber; and a sensor configured to monitor the turbidity of the slurry. Another aspect provides a semiconductor workpiece processing method including providing a semiconductor process chamber; supplying slurry to the semiconductor process chamber; and monitoring the turbidity of the slurry using a sensor.

Abstract: Integrated circuitry capacitors and methods of forming the same are described. In accordance with one implementation, a capacitor plate is formed and a conductive layer of material is formed thereove. Preferably, the conductive layer of material is more conductive than the material from which the capacitor plate is formed. In a preferred implementation, the conductive layer of material comprises a titanium or titanium-containing layer. In another preferred implementation, the capacitor plate comprises an inner capacitor plate having an outer surface with a generally roughened surface area. In one aspect of this implementation, the roughened surface area comprises hemispherical grain polysilicon. Capacitors formed in accordance with the invention are particularly well suited for use in dynamic random access memory (DRAM) circuitry.

Abstract: A vehicle door locking system including a latch mechanism (11) having an operative condition and a release condition, external and internal manually operable controls (14, 16) for releasing the latch mechanism, and controllable coupling means (15, 17) for determining whether or not the internal and/or external controls (16, 14) are linked to the latch mechanism (11); the system includes a control arrangement (21) responsive to locking input signals for determining the relationship between the controls (15, 17) and the latch mechanism (11).