Abstract: A system and a method for safeguarding wafers and photomasks. The system includes a container for storing an article, the article being a wafer or a photomask; a flashing unit for flashing light with a pre-determined light pattern; an anti-theft unit capable of performing an anti-theft function, the anti-theft unit being attached to the container; and a trigger unit electrically connected to the anti-theft unit for triggering the anti-theft function of the anti-theft unit, in response to detecting the pre-determined light pattern of the flashing unit. The method includes providing a container having an anti-theft unit capable of performing an anti-theft function; storing an article in the container, the article being a wafer or a photomask; providing a flashing light with a pre-determined light pattern; detecting the pre-determined light pattern; and performing the anti-theft function by the anti-theft unit, in response to detecting the pre-determined light pattern.

Abstract: The present invention discloses a method and apparatus for detecting timing constraint conflicts, the method comprising: receiving a timing constraint file; taking all test points in the timing constraint file as nodes, determining directed edges between the nodes and weights of the directed edges according to timing constraints relevant to the test points in the timing constraint file to establish a directed graph; searching for all directed cycles of the directed graph; and for each directed cycle, if the sum of the weights of the directed edges constituting the directed cycle satisfies a required condition, determining that a timing constraint conflict exists among the test points and the timing constraints constituting the directed cycle. The method and apparatus can automatically detect timing constraint conflicts with one hundred percent to reduce design turnaround time and engineer resources in ASIC projects.

Abstract: A Static Random Access Memory (SRAM) includes word lines WL, bit lines BL, address decoders that select one of the word lines WL in response to an address signal AD, a sense amplifier that is activated in response to a sense amplifier enable signal SAE, and a sense amplifier control circuit that generates the sense amplifier enable signal SAE. In this device, the more distant the word line WL is from the sense amplifier, the longer the sense amplifier control circuit sets the delay time of the sense amplifier enable signal SAE so that the more distant the word line WL is from the sense amplifier, the later the sense amplifier is activated.

Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.

Abstract: A method suitable for reducing side lobe printing in a photolithography process is enabled by the use of a barrier layer on top of a photoresist on a substrate. The barrier layer is absorbing at the imaging wavelength of the underlying photoresist and thus blocks the light from reaching the photoresist. A first exposure followed by a development in an aqueous base solution selectively removes a portion of the barrier layer to reveal a section of the underlying photoresist layer. At least a portion of the revealed section of the photoresist layer is then exposed and developed to form a patterned structure in the photoresist layer. The barrier layer can also be bleachable upon exposure and bake in the present invention.

Abstract: System, method, and program product analyze netlists for related electrical circuit designs by comparing predefined physical characteristics between the netlists. A baseline reference score is generated for one of the netlists and a normalized score is generated for the other netlist. The baseline reference score and the normalized score are used to generate a similarity score that is displayed on a display monitor. Preferably, the similarity score is displayed as a percentage.

Abstract: An interconnect structure including a lower interconnect level with a first dielectric layer having a first conductive material embedded therein; a dielectric capping layer located on the first dielectric layer and some portions of the first conductive material; an upper interconnect level including a second dielectric layer having at least one via opening filled with a second conductive material and at least one overlying line opening filled with the second conductive material disposed therein, wherein the at least one via opening is in contact with the first conductive material in the lower interconnect level by a via gouging feature; a dielectric liner on sidewalls of the at least one via opening; and a first diffusion barrier layer on sidewalls and a bottom of both the at least one via opening and the at least one overlying line opening. A method of forming the interconnect structure is also provided.

Abstract: Disclosed is a semiconductor article which includes a semiconductor base portion, a back end of the line (BEOL) wiring portion on the semiconductor base portion, a through silicon via and a guard ring. The semiconductor base portion is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having metallic wiring and insulating material. The BEOL wiring portion does not include a semiconductor material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor base portion. The guard ring surrounds the through silicon via in the BEOL wiring portion.

Abstract: An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.

Abstract: A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip.

Abstract: A method and structure of connecting at least two integrated circuits in a 3D arrangement by a through silicon via which simultaneously connects a connection pad in a first integrated circuit and a connection pad in a second integrated circuit.

Abstract: An apparatus and a method for enhancing a field of vision of a user with a visual impairment to help the user to navigate safely in the surroundings. The apparatus includes a body, at least one video device coupled to the body for recording a visual image of a physical environment surrounding the user, at least one monitor coupled to the body, a processor which receives signals from the at least one video device and operatively controls the at least one monitor to display the visual image recorded by the at least one video device, and a tunnel vision finder to determine the user's actual vision size. The method includes the step of determining the user's actual vision size, acquiring a visual image of a physical environment surrounding the user, processing the visual image, and displaying the visual image in the user's actual vision.

Abstract: Embodiments that dynamically conserve power in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more processors coupled with one or more NUCA cache elements. The NUCA cache elements may comprise one or more banks of cache memory, wherein ways of the cache are vertically distributed across multiple banks. To conserve power, the computing devices generally turn off groups of banks, in a sequential manner according to different power states, based on the access latencies of the banks. The computing devices may first turn off groups having the greatest access latencies. The computing devices may conserve additional power by turning of more groups of banks according to different power states, continuing to turn off groups with larger access latencies before turning off groups with the smaller access latencies.

Abstract: The present invention relates to planarization materials and methods of using the same for substrate planarization in photolithography. A planarization layer of a planarization composition is formed on a substrate. The planarization composition contains at least one aromatic monomer and at least one non-aromatic monomer. A substantially flat surface is brought into contact with the planarization layer. The planarization layer is cured by exposing to a first radiation or by baking. The substantially flat surface is then removed. A photoresist layer is formed on the planarization layer. The photoresist layer is exposed to a second radiation followed by development to form a relief image in the photoresist layer. The relief image is then transferred into the substrate.

Abstract: A method, computer program product, and system for enabling the merging of a plurality of instance variables into a new composite same-class instance having the same instance variables with values determined by a user. Same-class instances are arranged in tabular format and are provided with selection buttons to allow the user to make selections of the desired instance variable values.

Abstract: The present invention relates to a method for removing residues from open areas of a patterned substrate involving the steps of providing a layer of a developable anti-reflective coating (DBARC) over a substrate; providing a layer of a photoresist over said DBARC layer; pattern-wise exposing said photoresist layer and said DBARC layer to a radiation; developing said photoresist layer and said DBARC layer with a first developer to form patterned structures in said photoresist and DBARC layers; depositing a layer of a developer soluble material over said patterned structures; and removing said developer soluble material with a second developer.

Abstract: A method, system, and computer program product for simultaneous multi-channel upload of a file to one or more servers while ensuring data integrity. A validation scheme employs hashes to allow segments of the data file to be separately validated. Thus, if the upload process is interrupted or otherwise corrupted, segments of previously transferred data which have been transferred correctly may be validated, eliminating the need for re-transmission of that correctly transferred data. Preferably, a grid broker may be incorporated, allowing simultaneous multi-channel upload of data in a grid computing environment.

Abstract: A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.

Abstract: A method is described for measuring a dimension on a substrate, wherein a target pattern is provided with a nominal characteristic dimension that repeats at a primary pitch of period P, and has a pre-determined variation orthogonal to the primary direction. The target pattern formed on the substrate is then illuminated so that at least one non-zero diffracted order is detected. The response of the non-zero diffracted order to variation in the printed characteristic dimension relative to nominal is used to determine the dimension of interest, such as critical dimension or overlay, on the substrate. An apparatus for performing the method of the present invention includes an illumination source, a detector for detecting a non-zero diffracted order, and means for positioning the source relative to the target so that one or more non-zero diffracted orders from the target are detected at the detector.

Abstract: An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.