Abstract: A fault tolerant logic circuit capable of absorbing many D.C. and A.C. defects. The logic circuit employs a number of redundant logic gate circuits. The gate circuits are arranged in at least first and second interconnected signal paths. The logic gate circuits have two independent outputs. The two independent outputs are each connected to an input in a discrete one the first and second interconnected signal paths.

Abstract: A method and apparatus for fault testing a clock distribution network for A.C. and D.C. faults. The fault testing apparatus includes test latch circuit means and is adapted to initially test for D.C. (stuck) faults and to thereafter continuously monitor a plurality of clock signal lines to detect A.C. clock faults.

Abstract: Disclosed is a method and circuit for reducing and maintaining constant overshoot in a high speed driver. The circuit includes a predriver circuit which is driven single endedly and a driver circuit which is differentially driven by the predriver outputs. The predriver and the driver are differential pairs, with commonly controlled individual transistor current sources. A diode has been added in series with each emitter of the differential pairs. Schottky diodes are preferable because of their low capacitance. The diodes increase the input switching voltage (the smallest input voltage swing that will cause the outputs to fully switch) of the differential pair because they must also be switched on and off. The increase results in an increase in effective transition time, which results in smaller overshoots because the circuit is being switched slower. The output amplitude of the driver is set by a voltage which controls the current source currents of the commonly controlled current sources.

Abstract: Disclosed is an improved bit selection circuit for a RAM, in particular one employing CTS (complementary transistor switch) cells. The bit select circuitry includes interconnected first and second level matrix decoders, each memory column has a pair of bit lines, each pair of bit lines has connected thereto a bit select circuit, each of the bit select circuits being connected to an output of the second level decoder, a bit up-level clamp circuit connected to each of the bit select circuits of each pair of bit lines, each of the bit select circuits including a first circuit for increasing the speed of selection of the selected pair of lines, the bit up-level clamp circuit cooperating with the bit select circuit of the selected pair of bit lines for positively limiting the upper potential level of the selected pair of bit lines, and each of the bit select circuits including a second circuit for increasing the speed of deselection of the selected pair of bit lines.

Abstract: Disclosed is a Complementary Cascoded Logic (C.sup.2 L) Circuit which performs the AND-INVERT (AI) (or NAND) function. The AND function is implemented with input PNP transistors and the invert function is implemented with a first NPN transistor. An inverted NPN transistor serves as a current source for the first NPN. A first low voltage Schottky diode is serially connected between the emitter of the first NPN transistor and the emitter of the inverted NPN current source transistor. The first Schottky diode precludes, under certain conditions, simultaneous conduction of the first NPN transistor and the inverted transistor. Oppositely poled second and third low voltage Schottky diodes are utilized via an emitter follower output to provide an output voltage swing of V.sub.R .+-.V.sub.F, where V.sub.R is a reference voltage and V.sub.F is the potential drop across a Schottky diode. The low power high speed logic circuit (C.sup.2 L) has particular utility in redundant circuit applications.

Abstract: The logic circuit disclosed exhibits push-pull output characteristic by employing a saturated feedback technique. This approach allows for emitter follower like up level drive and transient low impedance down level drive. The disclosed saturated feedback technique improves capacitive drive capability, reduces both load and circuit delay and reduces circuit power dissipation.

Abstract: It is well known that the base width of a transistor has a direct bearing on transistor speed and the punch-through voltage. A solution to the transistor speed versus break down (punch through) voltage problem is disclosed. Output transistors are serially connected between power supply rails along with associated transistor base driving circuitry. The circuit arrangement ensures that the supply voltage divides between the series connected output transistors and prevents excessive voltage from being applied to each output transistor.

Abstract: A bipolar random access memory array including "end of write shut down circuit means" coupled to the write circuit means is disclosed. The "end of write shut down circuit means" is activated by and only functions as the written cell switches state. The "end of write circuit means" is coupled between the opposite bit line and preferably the write transistor of a write circuit of the write circuit means. The use of "the end of write circuit means" improves the overall operation of the memory and in particular the write operation thereof.

Abstract: A circuit for enhancing the ability of digital circuits to drive highly capacitive loads is disclosed. The circuit has particular utility when employed with logic circuits such as "TTL" (Transistor-Transistor Logic) and "DTL" (Diode-Transistor Logic).

Abstract: A read only memory utilizing a two-level cascoded current steering approach feeding a two-level common base isolation and sense amplifier network. The isolation network allows formation of a multi-way collector dot without deleterious effect upon the high speed current sensing operation. Single transistor cells with a common subcollector bed and common base rails as word lines make up the highly dense high speed array. The current source is provided by a current mirror circuit. The common-base, low impedance sense amplifier converts the sense current signal into a voltage swing which is then fed to the off-chip driver circuit via an emitter-follower pre-driver stage.

Abstract: Disclosed is a test system having circuitry for reducing off-chip driver switching (delta I) noise. The test system employs a tester connected to and electrically testing an integrated circuit chip. The integrated circuit chip has a plurality of input terminals for receiving an electrical test pattern from the tester. The integrated circuit chip also includes a plurality of output driver circuits having outputs connected to the tester. The test system is characterized in that the integrated circuit chip includes a driver sequencing network under control of the tester for sequentially conditioning the off-chip driver circuits for possible switching.

Abstract: An improved cascode current switch circuit particularly adapted for use in a data system or the like. The circuit provides a binary output, or an inhibit output under the control of a select/deselect input. The circuit includes interconnected upper and lower current switch circuits and is characterized by power reduction circuit means interconnecting the upper and lower current switches.

Abstract: A random access read/write memory array utilizing unclamped complementary transistor current switch (CTS) memory cells and having m columns and n rows. Each of the m columns of memory cells connected between the bit lines of a discrete one of m pairs of bit lines. Each of the n rows of memory cells connected between the word line and drain line of a discrete one of n pairs of word-drain lines. N identical write enhancement circuit means for enhancing the write operation of the memory array employing unclamped CTS memory cells. The write enhancement circuit means is preferably a single PN diode, or diode connected transistor, connected across each word/drain pair.

Abstract: The disclosure is directed to process and apparatus for the removal, site preparation, and replacement of any single connector pin contained within a sizeable array of closely spaced very small connector pins on an electronic packaging structure (substrate or module) without causing deleterious metallurgical effects either to the remaining pins or the ceramic substrate.

Abstract: Disclosed is a memory cell circuit for a gate array. The memory cell circuit is D.C. testable and has particular utility when employed in an integrated circuit containing "a mix of logic and array".Also disclosed is a memory array particularly adapted for use in an integrated circuit containing TTL logic circuits.

Abstract: An electronically selectable high performance data path switch which allows one input to drive two data buses or to have two inputs drive the two independently.

Abstract: An on-chip apparatus for generation of timing signals for a large scale integrated (LSI) chip or semiconductor memory array is disclosed. This apparatus may be used both during the production testing of the memory and during normal functional operation. In the testing environment it allows use of much less expensive peripheral test equipment, while also providing for much greater accuracy in determination of whether or not the memory array meets its timing specification. Use during normal functional operation (subsequent to use in the test environment) provides for a guarantee of defect free operation.

Abstract: The disclosure is directed to an improved random access memory (RAM). More particularly to improved bit selection circuitry for use in an array preferably employing unclamped CTS (Complementary Transistor Switch) type memory cells.

Abstract: A device for loading data in and reading data out of latch strings located in field replaceable units containing the circuitry of a data processing system realized in accordance with the Level-Scan Sensitive Design (LSSD) technique. Each field replaceable unit includes an addressing circuit. The addressing circuits are interconnected by a monitoring loop over which a configuration of address bits is serially transmitted by a control circuit. The data to be loaded and read out propagate in a data loop and are entered in a latch string under control of the addressing circuit.

Abstract: The disclosure is directed to an improved random access memory (RAM). More particularly to improved bit selection circuitry for use in an array employing CTS (Complementary Transistor Switch) type memory cells.