Abstract: Design rules and test structure are used to implement machine designs to thereby obviate during testing the need for mechanical probing of the chip, multichip module, card or board at a higher level of package. The design rules and test structure also provide a means of restricting the size of logic partitions on large logical structures to facilitate test pattern generation. A test mechanism is available on every chip to be packaged to drive test data on all chip outputs and observe test data on all chip inputs, independent of the logic function performed by the chip. A control mechanism is also provided to allow a chip to either perform its intended function or to act as a testing mechanism during package test. It is intended that the test mechanism built into every chip will be used in place of mechanical probes to perform a chip-in-place test and interchip wiring test of the package.

Abstract: A contact structure in a double polysilicon device is described in which direct shorts between overlying polysilicon conductors due to a "polysilicon void phenomenon" is overcome by patterning an appropriate etch stop between the conductors.

Abstract: An Exclusive OR circuit with at least two inputs (1 and 2) which exhibits a good immunity to noise. The circuit comprises diodes (D1 and D2) and two transistors (T1 and T2) which have their emitters connected to a reference voltage VR and produce AB at C1. Transistors (T 14 and T5) produce AB at C2, and output transistors (T13 and T6) produce ##STR1## at 3. This circuit can advantageously be used to realize a parity checking circuit.

Abstract: LSI circuitry conforming to LSSD rules and techniques usually requires at least a small portion of circuitry used only for check and test purposes. The disclosed circuitry meets the LSSD design rules and techniques and considerably reduces the test circuit overhead. The disclosure modifies the known shift register latch (SRL) strategy by replacing the SRL's by master latches in such a manner that the information contained in them is shifted in cascades, using the "division by two" principle for the master latches on the chip. The shift chain having only master latches is selected in response to shift clock signals. By consecutively shifting the respective cascade element, detailed information is obtained for all the master latches on the chip (without the information of the master latches temporarily used as slave latches during shifting) being lost in the cascade element. Level Sensitive Scan Design Rules and Techniques are extensively disclosed in the testing art. See for example: (1) U.S. Pat. No.

Abstract: After a controlled strong lowering of the word line potential for the purpose of addressing a cell, said potential is immediately recharged simultaneously increasing the potential on the N side of the two PNP injectors of the cell and causing the injector capacitances of the selected storage cells and the bit line capacitances to form a capacitive voltage divider, so that the bit lines connected thereto are recharged to different degrees by the different magnitudes of the injector capacitances. Thus, the differential signal formed on the bit lines is noticeably amplified by the supply of currents of different magnitudes.

Abstract: A contact structure in a double polysilicon device is described in which direct shorts between overlying polysilicon conductors due to a "polysilicon void phenomenon" is overcome by patterning an appropriate etch stop between the conductors.

Abstract: Disclosed is a self-aligned process for providing an improved bipolar transistor structure.The process includes the chemically etching of an intermediate insulating layer to undercut another top layer of a different insulating material in a self-aligned emitter process wherein the spacing of the emitter contact to the polysilicon base contact is reduced to a magnitude of approximately 0.2 to 0.3 micrometers. In addition, in the process an emitter plug is formed to block the emitter region from the heavy P+ ion dose implant of the extrinsic base.

Abstract: In a method for the generation, without dead time, of pulses appearing in successive pulse intervals, with a high time resolution of the pulse intervals and of the pulses, the signals characterizing start (IIN1A, IIN2A) and end (IIN1E, IIN2E) of a pulse interval are generated under storage control by an oscillator (1) for giving coarse time raster values, and a delay circuit (3, 4) series-arranged with the oscillator (1) and with selective (7, 8) delay circuit taps (5, 6) for giving fine time raster values. The signals characterizing the pulse intervals are alternatingly applied to one of two paths (path I, path II), such that the signal characterizing the respective pulse interval start coincides with the coarse time raster predetermined by the oscillator (1). For each path, the leading and trailing edge of a pulse to be generated within a pulse interval is derived via oscillator clock-driven counters (45, 47, 46 and 48) loadable with a count, upon a specific count being reached.

Abstract: An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc. The on chip delay regulator accomplishes this by comparing a periodic reference signal to a periodic on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip. For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock).

Abstract: Disclosed is a process for forming an improved bipolar transistor in a silicon substrate of a first conductivity type, said silicon substrate having a planar surface, a subcollector region of a second conductivity type formed in said substrate, an epitaxial layer of said second conductivity type formed on said planar surface of said substrate, and first, second and third spaced apart recessed oxide isolation regions extending from the planar surface of said epitaxial layer into said substrate, a subcollector reach-through region positioned between said second and third recessed oxide isolation regions, said subcollector reach-through region extending from said planar surface of said epitaxial layer to said subcollector region, said process including the following steps: deposit, using chemical vapor deposition techniques, a layer of doped polysilicon on the exposed surface of said substrate said dopant being of said first conductivity type; deposit, using chemical vapor deposition techniques a first layer of

Abstract: Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.

Abstract: In a process for producing a ceramic substrate for use in an electrical packaging structure, according to which (1) a substantially homogeneous ceramic mass, comprising alumina or glass ceramic, an organic bonding agent, a plasticizing agent, an emulsifying agent, a glass frit, and a solvent, is formed into a cohesive flat strip, (2) said strip is green dried and cut into desired size substrates, and (3) said substrates are sintered, the improvement comprising the step of lapping the substrates prior to the sintering step, whereby, after sintering, a smoother surface is obtained on said substrates than is obtained with substrates that have not been so lapped.

Abstract: A method and apparatus for testing large or very large scale integrated circuit packages is described. The testing equipment required for testing such packages is assumed to lack the number of channels necessary to connect one channel to each input/output of the unit under test. A computer program classifies all input terminals in a plurality of categories, each of which corresponds to particular circuit type and electric network configuration connected to that pin. A unique set of DC levels is defined prior to testing for each class of inputs. These levels are supplied by the tester channels, each of which drives a multitude of input pins that belong to the same category. The assignment of tester channels in the aforementioned arrangement is implemented by means of multiplexers that select for each pin the appropriate set of DC levels, and a memory buffer contained in the tester, with the DC test patterns stored wherein.

Abstract: The basic circuit (FIG. 2) includes an input device (A) driving two output transistors (B) and (C) which have different rise times [injection currents (I2, I3) or the input characteristics of the transistors (capacitors C2, C3) may be adjusted]. In a preferred embodiment (FIG. 3) differentiation is ensured by coupling a control transistor D to one of the output transistors (B) through a PNP transistor. If transistors (B) and (C) are cross-coupled, the circuit which is achieved is a bistable device. FIG. 4 shows the layout of the circuit of FIG. 3. Various applications in the synchronous logic circuit domain are described: T flip-flop (FIG. 8) and shift register (FIG. 9).

Abstract: Monolithically integrated storage arrangement with storage cells arranged in a matrix and consisting of two cross-coupled I.sup.2 L structures (T1, T2 and T1', T2') each in the manner of a flip-flop, wherein the read signal is derived from the charge carrier current reinjected into the injection zone (P1 or P1') of the respective conductive inverting transistor (T1 or T1') and thus into the connected bit line (BL0, BL1). The storage cells of a matrix line are selected via a common address line (X) coupled to the emitters (N1, N1') of the inverting transistors (T1, T1') of said storage cells.In spite of the fact that the structures have minimum area requirements, a high read signal is obtained by subdividing the address line (X) into two partial word lines (X1, X2). One partial word line (X1) is connected to all emitters (N1) of the inverting transistors (T1) of one I.sup.2 L structure of all storage cells of a matrix line.

Abstract: Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.

Abstract: An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layers containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction.

Abstract: A method for device fabrication utilizing a self-aligned process. A combination of advanced semiconductor processing techniques including Deep Dielectric Isolation by reactive-ion etching, etching and refilling, planarizing with oxides and resists, and differential thermal oxidation are used to form devices having small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls which extend from the epitaxial silicon surface through the N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3 .mu.m. A shallow oxide trench extends from the epitaxial silicon surface to the upper portion of the N+ subcollector and separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter.

Abstract: Disclosed is a method and apparatus (tester) for measuring the memory address access time (AAT) of RAM and ROS memories. The method and apparatus utilizes the data recirculation technique. The method is based on the following principle: memory (20, FIG. 9) is loaded with a predetermined data configuration, and, then, the output lines (d.O) of the memory are looped back and connected to the address lines (ad), through .tau.-delay lines (22); it is established that the memory oscillates with frequency ##EQU1## deducing therefrom the AAT time which is the required address access time, factor p being a function of the loaded configuration. The tester implementing such a method is illustrated in the drawing. In a first step, the data configuration contained in block (95) is transferred to memory (20), through multiplexer (94), to the appropriate addresses (di), through multiplexer (93), under the control of counter (92) and clock (91); the read/write selection line (21) is in "write" position.

Abstract: Semiconductor storage in which the current necessary for reading and/or writing the storage cells is generated simply by discharging input capacitances of the non-selected storage cells and is fed directly to the selected storage cells for reading and/or writing.