Abstract: In an integrated circuit an improved highly integrated semiconductor structure for providing a Schottky diode-resistor circuit configuration is disclosed. Although not limited thereto, the improved highly integrated semiconductor structure has particular utility when employed in a monolithic memory.

Abstract: A digitally regulated power supply for the corona charging unit of an electrostatic copying machine in which a sample of the ionic current of the corona unit is utilized in conjunction with a digital regulator to regulate the power supply establishing the charge of the corona. The digital regulator in conjunction with at least one pulse width modulated power supply permits very fast rise and fall times of the power supply current. Further, between duty cycles of the machine, the digital regulator stores a representation of the correct operating point of the corona charging unit determined in the immediately prior duty cycle. In the next duty cycle, the representation is utilized by the digital regulator to initially regulate the power supply.

Abstract: Improved integrated bipolar semiconductor structures and a method of fabricating same are disclosed. The logic circuit structures disclosed have enhanced density and speed power product. The teaching of the disclosed logic circuit structures includes utilization and extension of the known concepts of Current Hogging Injection Logic (CHIL) and Integrated Injection Logic (I.sup.2 L). The disclosed method of fabrication includes a minimum number of process steps, where each step is well within the state of the art and does not contain critical alignment problems.

Abstract: A gas encapsulated cooling module wherein at least one semiconductor chip to be cooled is supported on a substrate portion of the module the provision of a heat sink stud having a planar surface in thermal contact with a planar surface of the chip to be cooled, said stud being supported by a resilient thermally conductive bellow-like structure, whereby the planar surface of the stud is maintained in intimate thermal contact with the planar surface of the chip.

Abstract: A logical current switch responsive to a plurality of input logical signals having predetermined voltage swings and including in a first circuit arrangement parallel-connected bipolar transistors responsive to the logical signal levels of the input signals, and including in a second circuit arrangement a single bipolar transistor responsive to a logical function of the input signals via Schottky barrier diodes. Each of the above arrangements being connected with a further ground-biased transistor and including a Schottky barrier diode for coupling the emitter of the input signal responsive bipolar transistor to the emitter of the ground-biased bipolar transistor so as to result in circuits for producing complementary output signal level swings of a magnitude equal to the input logical signal voltage level swings.

Abstract: Level sensitive testing is performed on a generalized and modular logic with embedded array system that is utilized as an arithmetic/logical unit in a digital computer. Each arithmetic/logical unit of a computer is formed of arrangements of combinational logic networks, arrays and storage circuitry. The storage circuitry has the capability for performing scan-in/scan-out operations independently of the system input/output and controls. Using the scan capability, the method of the invention provides for the state of the storage circuitry to be preconditioned and independent of its prior history. Test patterns from an automatic test generator are cycled through the networks of combinational logic and arrays and their respective associated storage circuitry for removal through the scan arrangement to determine their fault status.

Abstract: The disclosure relates to LSSD systems for use in digital computers and the like. More particularly, to an organization of logic in such systems to render the clock networks testable with minimal overhead. The advantages of the practice of the invention are particularly apparent and enhanced when the invention is employed in a Level Sensitive Scan Design (LSSD) System generally of the type disclosed in U.S. Pat. No. 3,783,254 and U.S. patent application Ser. No. 701,052, filed June 30, 1976.

Abstract: Propagation delay testing is performed on a generalized and modular logic system that contains embedded arrays and can be used as arithmetic/logical/control unit in a digital computer or data processing system. Each such unit can be composed of combinatorial logic and storage circuitry. The storage circuitry may be of two types, randomly arranged latches, or arrays of storage cells. In the organization presented here the latches are arranged such that they have the capability of performing scan-in/scan-out operations independently of system control. Using this scan capability, the method of the invention provides for the state of the storage latches to be preconditioned and independent of prior circuit history. Selected propagation paths are sensitized by patterns from an automated test generator or designer supplied patterns.

Abstract: Disclosed is an improved clock generation network. The improved clock generation network is particularly adapted to, and has particular utility when employed in a Level Sensitive Logic System generally of the type disclosed in U.S. Pat. No. 3,783,254, of common assignee.The disclosed clock generation network also has particular utility in a Level Sensitive Embedded Array Logic System of the type disclosed in U.S. patent application Ser. No. 701,052, filed June 30, 1976, by Messrs. E. B. Eichelberger, E. I. Muehldorf, R. G. Walther and T. W. Williams and of common assignee.

Abstract: An improved wideband frequency multiplier characterized as follows: a saw-tooth signal generator supplying a saw-tooth wave having a frequency equal to the frequency to be multiplied, the level of the voltage wave varying between a reference level and a maximum which is related to the frequency to be multiplied; storage means for storing a voltage equal to, or closely approaching the maximum voltage value of the saw-tooth wave; a voltage divider having several outputs, each of which provides an output which is a given fraction of the stored voltage; a number of comparators each of which corresponds to and is coupled to an output of the voltage divider, each comparator comparing the instantaneous value of the saw-tooth voltage with the voltage supplied by the corresponding output of the voltage divider, and supplying a first level signal when said instantaneous value is lower than the voltage supplied by said corresponding output, and a second level signal when it is higher; and logical circuits combining the

Abstract: An improved random access word addressable monolithic memory having a storage cell for each binary bit of each binary word of storage capacity. The storage cells being arranged in groups. Each cell of any given group being adapted to store a binary bit corresponding to a given bit position of each word stored in said memory. Each cell of each group being connected via first and second bit lines to a sense amplifier. Each sense amplifier coupled to a reference voltage source. The magnitude of the reference voltage supplied by the reference voltage source bearing a substantially invariant mathematical relationship to first and second potentials manifested by said storage cells during a read mode.The storage cells may each be generally of the type disclosed and claimed in U.S. Pat. No. 3,423,737 entitled "Non Destructive Read Transistor Memory Cell" granted Jan. 21, 1969 to L. R. Harper and of common assignee with the instant application.

Abstract: Disclosed is a method of aligning a plurality of probes to a plurality of contacts, the contacts being arragned in a pattern on a substrate. The method includes the steps of powering one of a selected pattern of probes or a like pattern of selected contacts such that upon the selected patterns being in coincidence, the plurality of probes will be in contact with predetermined contacts on the substrate. This is accomplished by providing a circuit path through all of the other probes or contacts which are not powered and then bringing the plurality of probes into contact at random with the contacts of the substrate and then moving one of the substrate and probes until the selected patterns coincide as by indication of a completed circuit path between selected patterns.

Abstract: Disclosed is a novel device, named the Accordion Shift Register (A.S.R.) by virtue of an alternative expansion-compaction behavior of the digital data as it passes through the device.The A.S.R. provides an economical substitute for the conventional L1/L2 type Shift register used in a large scale integrated (LSI) logic structures known as the Level Sensitive Scan Design (LSSD). (See U.S. Pat. No. 3,783,254).

Abstract: A generalized and modular logic system is described for all arithmetic/logical units and their associated control storage and any other arrays. The logic system is partitioned into sections formed of combinational logic networks, storage circuitry, and arrays. The storage circuitry is sequential in operation and employs clocked dc latches. Two or more synchronous, non-overlapping, independent system clock trains are used to control the latches. The array is a rectangular array of storage element, M .times. N where, M is the number of words in the array and N is the number of bits in each word. The array may be read only, or it may be a read/write array. The array may be a programmable logic array (PLA). A single-sided delay dependency is imparted to the system. The feedback connections from the respective latch circuitry are made through combinational logic or an array to other latch circuitry. The clocking of the latches and of the array, if any, are such that the network may be operated in a race free mode.

Abstract: Disclosed is a chuck or handler for carrying thin, substantially planar workpieces intermediate process stations but while maintaining a clean air environment. The chuck includes a substantially planar surface having a workpiece receiving area thereon and a plurality of channels adjacent one edge of the planar surface but superimposed thereof. A conduit is in fluid communication with the channels and includes a foraminous diffuser element in the conduit to equalize the pressure of fluid entering the channels. A source of at least Class 100 air is connected to the conduit for supplying the channels with the gaseous media so that gaseous media emanating from the channels is essentially laminar and flows across the work area to create a surface attachment effect of the air or gaseous media over the workpiece on the work area.The purpose of this abstract is to enable the public and the Patent Office to determine rapidly the subject matter of the technical disclosure of the Application.

Abstract: A contactor structure employed in a high speed electronic test system for testing the electrical integrity of the conductive paths (or lines) in the packaging substrate prior to the mounting and connection thereto of the high circuit density monolithic devices. The contactor structure includes a semiconductor space transformer fabricated by large scale integration techniques and containing a plurality of discrete first integrated circuits. The first integrated circuits of the space transformer being respectively electrically connected to said electrical probes. Second integrated circuitry interconnecting said first integrated circuits is also contained within said semiconductor space transformer. Under control of said test system said second integrated circuitry selectively energizes, selected first and second ones of said first integrated circuits.

Abstract: The disclosure is directed to the circuitry and monolithic semiconductor structure of Current Hogging Injection Logic Configurations. More specifically the disclosure relates to a semiconductor arrangement for the basic components of a highly integratable, logic semiconductor circuit concept predicated on multicollector inverter transistors which are fed by means of a carrier injection into their emitter/base zones.

Abstract: A computer controlled manufacturing system employing random access semiconductor wafer storage in the fabrication of integrated circuit devices.A computer controlled manufacturing system for fabricating semiconductor wafers into large scale integrated circuit devices and wherein each semiconductor wafer has scored, or recorded thereon, distinct identifying indicia, such as a machine readable serial number. A plurality of concurrently operable semiconductor wafer processing stations are independently computer controlled. Each of the stations performing at least one discrete fabrication step.

Abstract: A method and circuit arrangement for operating an information store, in particular a monolithic information store, whose storage cells and address circuits comprise bipolar transistors which are not continuously subjected to full power. The monolithic information store is readily fabricated by known planar process technology, has increased density, has reduced read/write times, reduced cycle time, and reduced power dissipation.

Abstract: Disclosed is a Read/Write Buffer circuit for a random access memory integrated circuit chip based upon complementary enhancement mode field effect transistor technology.