Abstract: A method for fabricating NOR type memory cells of a nonvolatile memory device, floating gate insulating film, a floating gate electrode, a control gate insulating film, a control gate electrode, and an insulating film sequentially stacked in the shape of pattern on each of memory cell regions of a semiconductor substrate defined by an isolation film are formed; a source electrode and a drain electrode are formed in portions of the semiconductor substrate exposed at both sides of the gate electrode, a first etching barrier film is formed on the resultant; a first interlayer insulating film is formed on the first etching barrier film in a planarized fashion; a desired portion of the first interlayer insulating film is etched to form a first contact hole exposing the source and drain electrodes; a first conductive film in a planarized fashion is formed on the resultant to bury the first contact hole; the first conductive film is etched to form a source electrode line contacting the source electrode and a contact

Abstract: Provided is a method of manufacturing a semiconductor device having a stacked capacitor configured to reduce a step difference between a memory cell region and a logic circuit region adjacent thereto. In the method of manufacturing a semiconductor device, a sacrificial film removed after formation of the semiconductor device having a stacked capacitor, is preserved in the logic circuit region to be used as an interlayer insulating film. Thus, a step difference between a memory cell region having the capacitor and a logic circuit region, is removed, thereby facilitating formation of multi-layered interconnection wirings formed after forming the capacitor, and attaining fineness of the interconnection wirings.

Abstract: A device for cutting a row of interconnected rectangular plate-shaped workpieces into a plurality of individual rectangular units, includes a machine bed, and a sliding member disposed slidably on the machine bed and movable along a straight path. A rectangular work seat is disposed rotatably on the sliding member, and is rotatable about a vertical axis on the sliding member. The work seat has four sides, a length and a width. A mounting frame is disposed around the work seat, and defines a rectangular hole therein, which has four sides that are respectively parallel to the four sides of the work seat, and a length and a width that are respectively and slightly larger than those of the work seat. An adhesive sheet has an adhesive top surface with an outer peripheral portion that is adhered to a bottom surface of the mounting frame. The interconnected workpieces are adhered to the top surface of the adhesive sheet so as to be cut while disposed inside the mounting frame.

Abstract: A vertical blanking amplifier and bias clamp boost supply in accordance with the present invention uses the amplified vertical blanking signal to generate the boosted high voltage needed for powering the bias clamp circuits. A latch circuit is used to effectively lengthen the duration of the first vertical blanking pulse so as to ensure that the boosted power supply voltage is generated in the short time interval of one or two vertical scan intervals.

Abstract: The present invention relates to the field of digital broadcasting, and more particularly the insertion of digital video streams into other digital video streams. Compressed digital video streams, such as those compressed using the common MPEG-2 system, use a sequence of frames to compress a video sequence. Part of the encoding method to compress frames involves making predictions based on past or future frames. Where part of a compressed video stream is to be inserted into another existing video stream, problems may arise at the insertion point due to dependencies on past or future frames which occur outside of the insertion point. The effect of this is that the decoding process lacks information on which to make its predictions, and this could cause a decoder to reset or display frames out of order. The present invention overcomes this problem in a way which allows frame accurate insertion to be achieved without compromising quality.

Abstract: A voltage comparator with hysteresis that includes a differential amplifier, voltage divider circuits and a current mirror circuit. The input terminals of the two differential amplifier circuit branches are biased at unequal potentials by the voltage divider circuits. One voltage divider output voltage is fixed and the other is variable. The input terminal of the differential amplifier circuit branch biased at the fixed potential receives an AC-coupled input signal voltage. The sum of the input signal voltage and the fixed bias voltage is compared against the variable bias voltage. A current mirror circuit, which is activated during conduction by the differential amplifier circuit branch biased at the variable potential, shunts a portion of the current used by the voltage divider circuit that generates the variable potential. This causes the variable voltage divider output voltage to change, thereby introducing hysteresis into the voltage comparison performed by the differential amplifier.

Abstract: A closed feedback loop controls the slicing, or detecting, of an incoming data signal. Detected signal information about the positive and negative peaks of the incoming data signal is processed to generate positive and negative peak reference signals which serve as reference signal levels for establishing the thresholds at which signal slicing takes place.

Abstract: Two on-chip buses (OCBs) having respective standardized definitions are implemented on a multi-function system chip, with one of the OCB definitions being a subset of the other. System virtual components (VCs) are connected to the system OCB with a system virtual component interface or “bus wrapper”. “Peripheral” virtual components are connected to a peripheral OCB using respective standard interface blocks. Since the definition of the peripheral OCB is a subset of the system OCB, bridging between the two OCBs is relatively straightforward. The invention permits a “plug and play’ capability on behalf of all peripheral VC designs implemented according to the standard, such that the systems integrator may mix and match peripheral VCs without degradation of functionality or performance.

Abstract: A switched capacitor filter circuit having reduced offsets and providing offset compensation when used in a closed feedback loop includes a chopper stabilized amplified filter circuit which amplifies and low pass filters its input data signal to produce an output signal with an out of band signal frequency component which is at the chop signal frequency and represents an offset and 1/f noise of the chopper stabilized amplified filter circuit. An output switched capacitor filter circuit which is synchronized with the chopper stabilized amplified filter circuit filters this signal with a stopband filter frequency response that virtually eliminates such out of band signal frequency component. When used in a closed feedback loop, this filtered signal is used to generate an offset compensation signal that corresponds to the residual offset within the output signal resulting from the amplifying and filtering of the input data signal.

Abstract: A process for preparing EVA foam includes the steps of placing an amount of a kneaded composition in a mold such that the volume ratio of the kneaded composition to the mold cavity is about 0.15 to 0.5 and such that the kneaded composition is laid on the lower mold half, heating upper and lower mold halves of the mold in a manner that the temperatures of the upper and lower mold halves are not less than a reaction temperature, at which foaming and curing of the kneaded composition take place, and raising the temperature of the upper mold half to be higher than that of the lower mold half when the kneaded composition expands to a volume such that the volume ratio of the kneaded composition to the mold cavity is about 0.9 to 0.95.

Abstract: A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) enters the low power operational mode in which power consumption is reduced at least for the pipeline subcircuit, but without stopping the supply of clock signals to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode.

Abstract: A system and method for selective transfer of application data between storage devices in a computer system. Application data and non-application data are stored in a mass memory device. The application data and non-application data are received in a dump memory. Data in the dump memory is examined to identify the application data. A secondary address for the application data is derived. Application data from the dump memory indicated by the secondary address is received by a memory array. The application data indicated by the secondary address is parsed. Parsed application data is transferred from the memory array to dump memory. The parsed application data and the non-application data are transferred from the dump memory to the mass memory device. Finally, unexamined data is dumped from the mass memory device to the dump memory. The application data in one example represents a circuit to be simulated and the circuit could be described in a hardware description language such as VERILOG.

Abstract: An extended power ramp table for a power amplifier control loop in a time division multiple access (TDMA) communication system includes a power profile data table and a control data table. The power profile data are used to control transitions of the power amplifier circuit between its on and off states to minimize the number and power levels of spurious and other undesired signals generated by such on and off circuit state transitions. The control data are used to programmably control various performance characteristics of the control loop for the power amplifier circuit, such as controlling the gain of the driver amplifier for the power amplifier control (or reference) signal, controlling the gain and offset of the feedback amplifier for the control loop, and selectively providing a bias current for an external power detection diode. By making the control data user programmable, maximum flexibility in controlling the power amplifier control loop can be achieved.

Abstract: Dispensing apparatus 12 adapted for dispensing interleaved folded paper products 10 and 28 by means of a plurality of conventional dispensing perforations including one such perforation on the top face of a paper products container 14 and at least one other similar such perforation 20 on another face 22 of the container positioned at a point intermediate the height of the face.

Abstract: Disclosed is a ferroelectric random access memory including a plurality of bit lines extending in one direction, a plurality of plate electrode lines extending in another direction perpendicular to the one direction, a plurality of word lines extending in the same direction as the plate electrode lines, and a plurality of unit cells arranged in an M×N array. The unit cells are grouped into a plurality of unit cell groups, each unit cell group consists of a plurality of unit cells connected to associated bit lines such that the unit cells are interlaced in a row direction or in a column direction. A dummy cell group consists of a plurality of dummy cells each connected to an associated one of the bit lines at an optional position on the associated bit line.

Abstract: A ferroelectric random access memory including a plurality of bit lines extending in one direction, a plurality of word lines extending in another direction perpendicular to the one direction, and a plurality of unit cells arranged in an M×N array while being connected to associated ones of the lines. The unit cells are grouped into a plurality of unit cell groups. A dummy cell group comprises a plurality of dummy cells that are connected to an associated one of the bit lines of an optional position on the associated bit line.

Abstract: A switched capacitor filter circuit having reduced offsets and providing offset compensation when used in a closed feedback loop includes a chopper stabilized amplified filter circuit which amplifies and low pass filters its input data signal to produce an output signal with an out of band signal frequency component which is at the chop signal frequency and represents an offset and 1/f noise of the chopper stabilized amplified filter circuit. An output switched capacitor filter circuit which is synchronized with the chopper stabilized amplified filter circuit filters this signal with a stopband filter frequency response that virtually eliminates such out of band signal frequency component. The resulting output signal is then converted to a digital signal by an analog-to-digital conversion (ADC) circuit.

Abstract: An analog amplifier with a monotonic transfer function converts an incoming analog control voltage into multiple continuously variable discrete analog control voltages which are then used to control the respective gate biases of multiple MOS transistors. The MOS transistors are each connected in series with respective associated resistors and in a laddered parallel configuration with other serial transistor-resistor pairs. This creates a variable impedance circuit which, in accordance with the continuously variable discrete analog control voltages, exhibits a corresponding continuously variable circuit impedance in the form of a continuously variable resistance. This variable resistance forms part of the feedback circuit for controlling the gain of a noninverting operational amplifier circuit. This causes the ratio of the analog output and input signals of such operational amplifier circuit to define a monotonic transfer function.