Abstract: The invention relates to apparatus for and a method of remotely reversing the operation of a power piston in a power cylinder automatically to pump oil, corrosive or wax bearing fluids in response to unidirectional high pressure flow. The flow of high pressure fluid driving the piston in one direction may be reversed in the piston to drive the piston in the opposite direction at the end of the respective strokes by establishing collapsible chambers for the high pressure fluid within the piston. Each chamber is collapsed toward the end of alternate strokes by the reversing piston striking a stop slightly before the end of the stroke to partially collapse said chamber as a result of further movement of the power piston. At the conclusion of each stroke, all valving is closed and the high pressure entering the collapsed chamber now exerts force against the reversing piston, but since the reversing piston is against the stop, the force is oppositely directed to reverse the direction of the power piston.

Abstract: The invention provides a unique sub-micron dimensioned resistor and methods of making the same, wherein hundreds of such resistors may be fabricated on a single chip with each comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Spaced apart slots made in the substrate permit the introduction of orientation dependent etching fluid therein to at least substantially etch semi-arrays of active regions of the substrate away from the substrate except for spaced apart supports therealong. Oxidation serves to support the semi-arrays and subsequent steps directly from the substrate or by webs of oxidation along the tops of the semi-arrays connected to the substrate.

Abstract: The invention provides a unique sub-micron dimensioned NPN type transistor and method of making the same, wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Spaced apart slots made in the substrate permit the introduction of orientation dependent etching fluid therein to at least substantially etch semi-arrays of active regions of the substrate away from the substrate except for spaced apart supports therealong. Oxidation serves to support the semi-arrays and subsequent steps directly from the substrate or by webs of oxidation along the tops of the semi-arrays connected to the substrate.

Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices. The use of materials in successive layers having different etch characteristics permits selective oxidation of desired portions only of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability.

Abstract: An array of hundreds of devices may be simultaneously processed on a chip to sub-micron dimensions by establishing tiny active regions for each transistor surrounded by field oxide filled moats or slotted regions, wherein the slots are utilized to dope the substrate within the active region. The P type substrate is double energy arsenic planted through one surface to establish a N region to a given depth. This surface is oxidized and photoresist masked conventionally to open regions for the slots which are ion milled or ODE etched to a given depth. P+ regions are established by the slots by ion implanting at an angle such that the entire depth of the slot is not doped but rather the doping is confined to a region within the double energy N implanted depth. Drive-in diffusion enlarges the P+ areas for the emitter and collector and oxidation fills the moat insulating regions around the active area.

Abstract: The invention is a punch through voltage regulator having an active region formed on a substrate by any one of four different methods. Each method includes recessing the substrate substantially along the periphery of the regulator active region, selectively doping the regulator active region through portions of the recess, filling the recesses with substrate oxide to isolate the active region from the substrate and forming conductors to selectively doped portions of the active region to serve as electrode connections. For P doped substrates N type doping is introduced via the recesses and in a second method the recesses are deepened and P type doping is introduced into the substrate to change the doping in the active region. For N doped substrates P type doping is introduced via the recesses and when the recesses are deepened in the fourth method, N type doping is introduced into the substrate to change the doping of the active portion.

Abstract: An improvement in the method of forming polymerization resists by directing high energy particles such as electron beams along a path across a vacuum chamber and onto polymerizable molecular species at a substrate surface with sufficient energy to polymerize the polymerizable molecular species in situ is provided, comprising maintaining a chamber-isolated relatively higher pressure layer of polymerizable molecular species vapor locally at the substrate surface during, e.g. electron beam exposure to form the resist while maintaining the beam path free of polymerizable molecular species during beam traverse of the chamber. Polymerization resist generation apparatus is also provided comprising a high energy particle, e.g.

Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of desired portions only of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability.

Abstract: The invention provides a unique sub-micron dimensioned NPN type transistor and method of making the same wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Slots made in the substrate permit angle evaporation of etch-resist to protect the active region while it is disconnected from the substrate by etching therebeneath via the slots.

Abstract: The invention is a transistor or array thereof and method for producing same in sub-micron dimensions on a silicon substrate doped P or N type by forming slots in spaced apart relation across the substrate to define semi-arrays of V shaped intermediate regions which will become a plurality of transistors. Silicon oxide fills these slots and separates the transistor regions from the substrate. Orthogonal slots divide the semi-arrays into individual transistor active regions which are doped by one of N or P doping introduced into each active regions via the orthogonal slots and driven in to comprise the emitter and collector regions on respective sides of original substrate comprising the base regions. Metallization patterns complete electrical connections to the emitter base and collector regions and silicon oxide substantially covers the periphery of each active region for total isolation.

Abstract: The invention comprises a connection array for establishing a plurality of electrical connections between circuit pads of a support, such as a circuit board, and contacts of an electrical housing, such as a hermetic chip carrier, wherein the contacts comprise semi-circular vertical indentations in the housing periphery with each indentation having a conductive layer therein. A plurality of pillars, which may be electroplated, extend vertically above the support in an array respectively corresponding to the outline of the indentations with each pillar being connected to different pad of the support and the pillars having dimensions to permit at least partial entry into the indentations whereby solder may be introduced between the pillars and associated conductive layers to establish visible and inspectable electrical connections therebetween.

Abstract: The present invention comprises a unique FET with resistor in its drain lead of undoped polysilicon which may be characterized by high resistance in the absence of the application of a biasing voltage across the FET and the resistor when the FET is conducting, which biasing voltage irreversibly changes the resistor to a high state of conductivity thereby selectively providing the two logic states. This device may comprise a redundant cell for a ROM memory and may be uniquely fabricated utilizing VLSI MOS processing steps to provide a new manufacturing process.

Abstract: The invention is a sub-micron dielectrically isolated transistor and method of making the same wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by a field oxide region, N+ spaced-apart doped portions within said regions and a P+ doped portion of said region spaced from each N+ doped portions, and electrical connections to the base P+ portion and the collector and emitter N+ portions. These regions are established by first forming boundary recesses about each active portion where a transistor will be formed, depositing arsenic in the recesses to form N+ regions in the transistor-active region adjacent the recesses, deepening the recesses, diffusing boron into the deepened recesses to dope the substrate P-type beneath the N+ regions and also between the N+ regions, and patterning and metallizing the substrate to develop the electrical connections of the base, emitter and collector electrodes.

Abstract: An array of hundreds of devices may be simultaneously processed on a chip to sub-micron dimensions by establishing tiny active regions for each transistor surrounded by field oxide filled motes or slotted regions, wherein the slots are utilized to dope the substrate within the action region. The N type substrate is double energy boron planted through one surface to establish a P region to a given depth. This surface is oxidized and photoresist masked conventionally to open regions for the slots which are ion milled or ODE etched to a given depth. N+ regions are established by the slots by ion implanting at an angle such that the entire depth of the slot is not doped but rather the doping is confined to a region within the double energy P implanted depth. Drive-in diffusion enlarges the N+ areas for the emitter and collecter and oxidation fills the mote insulating regions around the active area.

Abstract: The invention is a thin film alloy source utilizing a supply of alloy wire selected for deposition onto a substrate. The wire is advanced through an induction heating means at a controlled rate for evaporation onto the substrate. Detection of the meniscus height or temperature of the end of the wire being evaporated yields a control signal for operating the control wire feed mechanism for advancing the wire at a rate to provide a predetermined coating thickness.

Abstract: The present invention comprises a unique FET with resistor in its drain lead of undoped polysilicon which may be characterized by high resistance in the absence of the application of a biasing voltage across the FET and the resistor when the FET is conducting, which biasing voltage irreversibly changes the resistor to a high state of conductivity thereby selectively providing the two logic states. This device may comprise a redundant cell for a ROM memory and may be uniquely fabricated utilizing VLSI MOS processing steps to provide a new manufacturing process.

Abstract: The invention is an apparatus and method for achieving thin film deposition, of uniform composition, from evaporated alloys. A source of wire alloy, selected for the particular thin film deposition on a substrate, is continuously fed through a region of high speed electron bombardment confined to an end of the wire, for evaporation of the wire in the vicinity of the substrate. An ion flux detector controls the rate of feeding of the wire source in accordance with the detected flux to lay down a uniform thin film of predetermined thickness. A high potential is established between the wire and the source of the electrons and the liberated electrons are guided by the electric field toward the end of the wire being evaporated, which serves as an anode.

Abstract: The invention applies a reference voltage to a responsive means for producing a signal of one type in the absence of a semi-conductor at the addressed memory location, and applies a voltage less than the reference voltage to the responsive means for producing a signal of another type if a semi-conductor is present at the addressed memory location.The reference voltage is produced by a novel constant low voltage variable current source. The responsive means comprises inverter amplifier means. The reference voltage centers the small voltage swing on the bit line to the trigger point of the inverter amplifier. The means for determining the magnitude of voltage applied to the inverter is a pull up FET in series with the memory FET at the addressed location.

Abstract: The invention is a method of minimizing redeposition of thin film material being removed by ion impact via a patterned resist mask, which invention determines the resist mask etching rates in selected atmospheres and determines the material etching rates in selected atmospheres. Then the mask thickness is selected relative to the material thickness, the ambient gases, and the ion beam parameters to cause the resist mask to be faceted to the edges of underlying material as the unprotected layer is removed such that no resist walls remain to receive redeposited material.

Abstract: An apparatus and automated process to improve the accuracy and reduce the time, cost, and effort necessary to prepare reproduction artwork for charts is disclosed. A numerically or computer controlled imaging system is used to expose photographic film or emulsion with specially prepared halftone pattern symbols. This allows a computer to be used to select both the symbol and location, instead of slow and costly manual methods. Greatest benefits accrue when the final chart is to be in color. One sheet of film per primary color is exposed using a few basic symbols, which are then combined to yield a wide range of color in the symbols of the final chart. Typically, the final product of this process is one or more sheets of monochromatic film used as masters for a color printing or color key process. Further, a method is described to avoid erroneous density (and resultant color) changes where halftone symbols overlap, as well as various other methods to improve legibility and produceability of the charts.