Abstract: The invention includes methods and apparatus for providing relatively long conductors on integrated chips with substantially reduced RC time constants. The preferred mode utilizes a substrate having a metallization pattern wherein etching or milling into the substrate creates a cavity with a metallization conductor disposed in the mouth of the cavity, said cavity being metallized to provide the second conductor. A similar structure may be formed by utilizing orientation dependent etchant which attacks the (111) surface much quicker than the (100) surface to provide an etched V-shaped cavity wherein the first conductor is still an elongated metallization segment in the mouth of the V, and the V is metallized to provide the second conductor.

Abstract: The invention is a thin film alloy source utilizing a supply of alloy wire selected for deposition onto a substrate. The wire is advanced through an induction heating means at a controlled rate for evaporation onto the substrate. Detection of the meniscus height or temperature of the end of the wire being evpaorated yields a control signal for operating the control wire feed mechanism for advancing the wire at a rate to provide a predetermined coating thickness.

Abstract: The invention includes methods and apparatus for providing relatively long conductors on integrated chips with substantially reduced RC time constants. The preferred mode utilizes a substrate having a metallization pattern wherein etching or milling into the substrate creates a cavity with a metallization conductor disposed in the mouth of the cavity, said cavity being metallized to provide the second conductor. A similar structure may be formed by utilizing orientation dependent etchant which attacks the (111) surface much quicker than the (100) surface to provide an etched V-shaped cavity wherein the first conductor is still an elongated metallization segment in the mouth of the V, and the V is metallized to provide the second conductor.

Abstract: The invention is an apparatus and method for achieving thin film deposition, of uniform composition, from evaporated alloys. A source of wire alloy, selected for the particular thin film deposition on a substrate, is continuously fed through a region of high speed electron bombardment confined to an end of the wire, for evaporation of the wire in the vicinity of the substrate. An ion flux detector controls the rate of feeding of the wire source in accordance with the detected flux to lay down a uniform thin film of predetermined thickness. A high potential is established between the wire and the source of the electrons and the liberated electrons are guided by the electric field toward the end of the wire being evaporated, which serves as an anode.

Abstract: An improvement in the method of forming polymerization resists by directing high energy particles such as electron beams along a path across a vacuum chamber and onto polymerizable molecular species at a substrate surface with sufficient energy to polymerize the polymerizable molecular species in situ is provided, comprising maintaining a chamber-isolated relatively higher pressure layer of polymerizable molecular species vapor locally at the substrate surface during, e.g. electron beam exposure to form the resist while maintaining the beam path free of polymerizable molecular species during beam traverse of the chamber. Polymerization resist generation apparatus is also provided comprising a high energy particle, e.g.

Abstract: A circuit for producing a signal of one type in the absence of a semiconductor at an addressed memory location and a signal of another type in the presence of the semiconductor includes a constant voltage reference source to supply a variable current to a pull up FET. The pull up FET is connected to be in series with the memory semiconductor when it is present in the circuit, and operates to supply a low level voltage to an output amplifier when the semiconductor is present and a high level voltage when the semiconductor is not present. The low level voltage is centered about the trigger point of the amplifier, so that the bit line swing from the memory semiconductor produces a full MOS output from the amplifier.

Abstract: A voltage and temperature insensitive reference circuit voltage source for predetermining the proportion of supply voltage to constitute the output voltage including a pull-up device and a pull-down device connected between a source of supply voltage and a reference point. A two element biasing circuit is connected between the source and the pull-down device which is connected to the reference point with the pull-up device comprising a FET having a gate. A connection extends from the biasing circuit at a point between its elements to the gate. An output connection extends from the junction of the pull-up and pull-down device. One of the elements which is connected between the source and the other of the elements is characterized by high resistance relative to the other of the elements whereby the proportion of voltage available at the output connection remains substantially constant regardless of source voltage variation and ambient temperature.

Abstract: An LED matrix display is disclosed having a plurality of light-emitting diodes of appropriate size, shape and spacing to emulate the appearance of lighted objects in substantially continuous motion. Application and duration of control signals are controlled by a programmed microprocessor to produce a video-like display primarily suitable for use in conjunction with hand-held electronic games.

Abstract: An electronic card game simulation apparatus adapted primarily for portable hand-held use by a player. A microprogrammed MOS/LSI device receives selection signals generated by means of a keyboard to which a player has access, and controls the progress of the card game in response thereto and in accordance with established game rules as programmed in a storage device such as a read only memory unit. A display device, such as a plurality of seven-segment fluorescent displays, indicates the identity of simulated playing cards dealt randomly from a full 52-card deck of simulated cards as the game progresses. In a preferred embodiment, the microprogrammed device includes memory capacity, arithmetic capability, and appropriate programming to permit a player to play the well known game of Blackjack against a phantom dealer and to place bets which are automatically added or subtracted from a previously established stake in accordance with the outcome of each hand.

Abstract: The invention is a method of minimizing redeposition of thin film material being removed by ion impact via a patterned resist mask, which invention determines the resist mask etching rates in selected atmospheres and determines the material etching rates in selected atmospheres. Then the mask thickness is selected relative to the material thickness, the ambient gases, and the ion beam parameters to cause the resist mask to be faceted to the edges of underlying material as the unprotected layer is removed such that no resist walls remain to receive redeposited material.

Abstract: The invention is a method of sloping thin film materials so that smooth, continuous films may be deposited thereon. By controlling the thickness of resist mask over the materials (as for patterning) relative to ion milling or sputter etching parameters, repeatable slopes and linewidths may be achieved. For use in bubble memory fabrication, the sloping of conductor walls enables propagation bars to be laid down in crossing over relation thereto while enhancing yield.

Abstract: Reheating the cooled wafer product of the known method of forming thermal oxide surface passivation layers on GaAs crystal wafers, i.e. heating the wafer in contact with thermally vaporized As.sub.2 O.sub.3 in a substantially oxygen free closed vessel at a reaction temperature in excess of 450 degrees, from a temperature lower than the reaction temperature to a temperature higher than the reaction temperature and in the presence of free oxygen increases the compositional, physical and electrical uniformity of the surface layer.

Abstract: An improved layout for controlling the channel length of silicon gate, enhancement and depletion pull-up field effect transistor devices. The improved layout enables a transistor device to be fabricated with minimal size and at minimum channel length tolerance.

Abstract: The invention is a work holding system for adjustably receiving and holding printed circuit boards for automatic machine component insertion. It includes a frame and a plurality of mutually cooperative adjustable board holders. The frame is U-shaped and is made up of framing members each having a linear scale affixed thereto. An adjustably positionable framing member extends across the U and is slidable along the opposed framing members toward and away from the base framing member forming the bottom of the U. Means are provided for indexing, locking the adjustably positionable member to the frame in any desired position. A linear scale is also carried by the adjustably positionable member and all scales have a common datum. The frame carries indexing means to index it to the machine which inserts components. A number of adjustable board holders are slidably carried by the base framing member and the adjustably positionable framing member to receive circuit boards therebetween.

Abstract: The invention is an apparatus and method for aligning a very fine wire relative to a workpiece. It comprises an alignment fixture supporting a pair of spaced-apart lead screws for receiving the wire in the threads thereof. The wire is affixed to spacer arms oppositely protruding from the fixture and spans the spacing between the screws. The workpiece is supported between the spacer arms and may be raised or lowered to provide alignment with the wire which is then translated or oriented by turning either or both of the lead screws until the relative alignment is achieved. The wire is affixed to each of the arms in a slackened condition and a tiny weight is suspended from the wire for yieldably tensioning the same across the threads, but providing for translation without fracture.

Abstract: There is shown and described a memory array using MNOS/MOS transistors. The memory devices are nonvolatile, metal-nitride-oxide-semiconductor (MNOS) variable threshold voltage transistors and the metal-oxide semiconductor (MOS) input-output devices exhibit fixed threshold voltages. The MOS devices are fabricated first and the MNOS memory devices are fabricated thereafter. This memory gate last (MGL) arrangement eliminates the need for high temperature process steps after the formation of the MNOS device gate dielectric in the array devices. This operation results in an MNOS/MOS memory array which exhibits excellent ionizing radiation hardness characteristics as well as memory properties which are improved over present radiation hardened MNOS/MOS arrays.

Abstract: The invention is a method and apparatus for multiplexing liquid crystal displays of increased numbers of alphanumeric characters without shadowing or flicker and minimizes contrast degradation. Bipolar segment voltages are interrelated to bipolar tri-level backplane voltages for logical selection of voltage differences across the segments to provide either energization or less than threshold voltage application. The polarities of the bipolar voltages are automatically reversed at the end of each cycle of sequential application of backplane voltages to all backplanes to avoid metallization plating problems in the display. Power level shift is accomplished in the logic stage for the display, and CMOS active gate elements are used in lieu of power consuming resistive networks for a total power requirement of less than 5 milliwatts to multiplex and drive up to 7 characters of 16 segments each. Simplified interfacing with a microprocessor is provided using standard 8 bit bus and control signals.

Abstract: Semiconductor devices with gate dimensions as small as 0.25 microns square have been fabricated using electron beam lithography and dry processing techniques. In particular, silicon gate, N-channel, metal-oxide-semiconductor (NMOS) field-effect-transistors (FET) have been produced. The devices and the process are especially adapted to bulk silicon based transistors.

Abstract: A digital-to-analog optical recorder incorporating both CCD and integrated optics technologies which is fabricated as a single integral unit including an electro-optical layer portion and a semiconductor layer portion. Sampling circuits and digital-to-analog converters are implemented on the semiconductor layer portion using CCD technology, and a plurality of optical channel waveguides and electro-optical modulators are implemented on the electro-optical layer portion. Each digital signal is converted into two complementary light spots at the output of the recorder.

Abstract: An improved static metal oxide semiconductor (MOS) input circuit having particular utility as a TTL input receiver, is fabricated from enhancement and depletion-type field effect transistors (FETs). The input circuit is adapted to produce positive feedback to adjust the on-resistance ratios of some of the circuit transistor devices, whereby hysteresis is developed. By virtue of the hysteresis, an extended noise margin is provided at the circuit input terminal so that MOS logic level output signals are clearly distinguishable from one another at the circuit output terminal.