Abstract: A simulator of WBEM/CIM indication providers conforming to the CIM Indication Provider object specification simulates both the CIM indication provider and the means to drive the associated CIM events. The simulator comprises three functionally unique pieces: one or more CIM indication provider drivers, one or more CIM event trigger drivers, and a control application. This modularization creates flexibility in configuring the simulator to stress test different aspects of an operating system's underlying support for CIM indications. Modularization also makes the simulator design operating system independent. Provision is made in the simulation for generation of additional CIM events as background activity on the operating system.

Abstract: Disclosed is a method of minimizing clock uncertainty using a multi-level de-skewing technique. The method includes the steps of obtaining a chip wherein at least a portion of the chip has a regular array of buffers on multiple levels, the buffers being driven by first drivers and the first drivers being driven by second drivers; grouping the buffers in a first direction to create clusters with the same number of buffer inputs, wherein if there are not the same number of buffer inputs in each cluster, then adding dummy buffers to the cluster with a deficient number of buffer inputs; wiring outputs of the first drivers together in a second direction, wherein the first and second directions are orthogonal; and wiring outputs of the second together in the second direction.

Abstract: A MCM system board uses a stiffener arrangement to enhance mechanical, thermo and electrical properties by incorporating an LGA compression connector in a computer system. The present designs of large scale computing systems (LSCS) in IBM use a MCM that is attached to a system board and held together by a stiffening frame. Due to the nature of the manufacturing of the system board, there can be significant gaps formed in the mounting area of the MCM between the board and the stiffener. A method is described that not only fills the void, it also, in addition promotes thermo conduction of excess heat away from the MCM and at the same time promotes enhanced electrical properties of the LGA connections of the MCM to the system board.

Abstract: A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester.

Abstract: A method for preprocessing tie net routing data organizes the data into a plurality of tie nets each based on an optimal connection path between a pin or set of pins and the power grid. The router then routs the data embodying the thusly-simplified plurality of tie nets. Once the routing is complete, post processor takes the routed design and returns it to its original net list state while keeping the routing solution.

Abstract: A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.

Abstract: Disclosed is a method of estimating interconnect wire parasitics in integrated circuits which includes obtaining a circuit layout having circuit components placed thereon including source input/output (I/O) pins and sink I/O pins, the circuit layout having a circuit hierarchy, bubbling up of the I/O pins until all I/O pins are on a same level of the circuit hierarchy, and then estimating interconnect segments to be employed in interconnecting at least some circuit components of the placed circuit components of the circuit layout. Also disclosed is a circuit design system and program storage device.

Abstract: This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.

Abstract: A system for improving a logic circuit may include a processor, and a logic circuit analyzer in communication with the processor to model a plurality of nets. The system may also include an interface in communication with the logic circuit analyzer to select a target slack-value for each one of the plurality of nets. The logic circuit analyzer may determine a slack-value for each net. In addition, the logic circuit analyzer may selectively reduce resistive-capacitive delay for each net respectively if the determined slack-value is less than the target slack-value for each respective net.

Abstract: In the course of unit timing, there exists the possibility for a non-compute (N/C) on a particular net in an IC chip design, which could be caused by numerous things, including but not limited to a pin being tied to power, a floating output, or invalid timing test for a given phase at a test point. A process automatically verifies that all non-computes are understood and exist for valid reasons, in order to ensure all necessary paths are being timed. The process takes a conventional Comprehensive Report output of a unit timing run and generates macro specific N/C reports for designers to review and sign off on.

Abstract: A data processing system includes a data storage unit for storing data sets accessible to a user upon receipt of permission. The data processing system restricts access to data sets by requiring a username and then requiring a password to obtain permission for access to a data set stored in a data storage unit. The system is adapted to support use of more than one said password associated with a username; and each of those passwords associated with that username permits a distinct level of access to a particular data set, whereas other passwords can provide different levels of access to any data set assigned thereto.

Abstract: An integrated circuit chip has new Frequency dependent RLC extraction and modeling providing on chip integrity and noise verification and the extraction and modeling employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.

Abstract: To provide a method and a system for creating a mini time key from a time key, a plurality of mini time keys are created within a unit time period. First, a unit time decryption key is prepared immediately after the unit time is created. Then, the last mini time key is created by applying a one-way function to the unit time decryption key. A desired mini time key is created by applying the one-way function to a mini time key following the desired mini time key. In other words, the mini time keys are created as a timed series arranged in a descending order beginning with the last mini time key. In this manner, even when a specific mini time key is externally leaked for a specific reason, a following mini time key in a timed series can not be created by using this mini time key. In addition, even when the mini time keys are sequentially published, the security of the unit time decryption key is maintained.

Abstract: A wiring structure for clock signals has two or more parallel clock signal wires disposed in adjacent power wire bays that span the distance between the sinks to which the clock signal wires are to be coupled. The parallel clock signal wires are shorted one to another by stubs placed at locations in order to time the clock wiring structure. The delay tuning of the structure is obtained by the discrete movement of wiring stubs between the wiring bays of the pre-defined power grid.

Abstract: A method for identifying and modifying, in a VLSI hierarchical chip design, parent buffer placements which lead to wiring track inefficiencies with respect to data flow and the parent placement area geometry. Parent placement area is reviewed and a subset is categorized and distinguished as either horizontal slots or vertical slots. Buffer to buffer data flow is reviewed for cases where data flow direction is either strongly horizontal or strongly vertical. Situations where buffer to buffer data flow is oriented in the same direction as the parent placement slots in which the buffers reside are reported. Additionally, an attempt is made to find a valid placement location for the buffers excluding parent placement areas oriented in the same direction as the data flow.

Abstract: A data input latch and clocking method and apparatus for high performance SRAM in which an L1 data input latch is controlled by a logical combination of the normal local clock buffer clock signal and the local array clock buffer clock signal. This logical combination of clock signals minimizes the hold time of the L1 latch provides a fast cycle time in which the SRAM macro can process successive write instructions while avoiding early mode issues.

Abstract: The on-chip power supply noise sensor detects high frequency overshoots and undershoots of the power supply voltage. By creating two identical current sources and attaching a time constant circuit to only one, the high frequency transient behavior differs while the low frequency behavior is equivalent. By comparing these currents, the magnitude of very high frequency power supply noise can be sensed and used to either set latches or add to a digital counter. This has the advantage of directly sensing the power supply noise in a manner that does not require calibration. Also, since the sensor requires only one power supply, it can be used anywhere on a chip. Finally, it filters out any lower frequency noise that is not interesting to the circuit designer and can be tuned to detect down to whatever frequency is needed.

Abstract: Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.

Abstract: A method and apparatus for generating a voltage that is proportional to an absolute temperature (PTAT voltage). A current generator for generating a current that is proportional to absolute temperature (PTAT current) has an internal resistance and two diodes. The PTAT current is proportional to the resistance, and the temperature coefficient of the PTAT current is defined by the ratio of diode current densities. A feedback circuit has a source follower that is connected to the current generator for driving the output node with a regulated PTAT current wherein the PTAT current is mirrored accurately, providing a constant Vref.

Abstract: System-accessible frequency measuring circuits and procedures permit on-chip testing of the oscillators and provide test results observable off chip via LSSD scan paths. This allows a rapid ensemble of ring oscillators in a standard ASIC test flow without the need for on chip analog test equipment (the test apparatus has effectively been created on device and can be digitally configured, operated and read). Frequency measuring logic that can 1) functionally operate to measure the frequency of the ring oscillators; 2) participate in traditional logical tests such as LSSD and LBIST to verify that the circuit is manufactured correctly and is likely to operate and 3) operate in a special ring-oscillator test mode, that allows the logic to operate on a tester very similarly to the way it does functionally. In this mode, the frequency measuring logic can be scanned to a specific state, started by pulsing a digital I/O, and the measured analog value can be scanned out sometime later after the test has completed.