Patents Represented by Attorney, Agent or Law Firm William A. Kinnaman, Jr.
  • Patent number: 7243293
    Abstract: An (18, 9) error correction code that is simultaneously double error correcting and triple error detecting is disclosed. The code is defined by the following parity check matrix: ? 1 3 ? ? ? ? 1 6 ? ? ? 1 12 ? ? ? 1 7 ? ? ? ? 1 14 ? ? ? 1 11 ? ? ? 1 5 ? ? ? 1 1 ? ? ? 1 2 ? ? ? 1 4 ? ? ? 1 8 ? ? ? ? 1 16 ? ? ? 1 15 ? ? ? 1 13 ? ? ? 1 9 ? ? ? 0 ? 1 ? ? ? 1 10 ? ? 1 1 , where ? is a root of the polynomial x17?1 in the finite field of 256 elements. Logic circuitry for efficiently determining the locations of single and double errors as well as for detecting the presence of uncorrectable errors is also disclosed.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: July 10, 2007
    Assignee: International Business Machines Corporation
    Inventor: Chin-Long Chen
  • Patent number: 7233366
    Abstract: To allow a telop image to be displayed appropriately even when color information and transparency information for the telop image are transmitted over a network, the present invention provides a telop image sending/receiving system comprising a telop image sending apparatus and a telop image receiving apparatus in which the telop image sending apparatus has an OA fill signal input section for inputting color information for a telop image, an OA key signal input section for inputting transparency information for the telop image, an association storage section for storing color information and transparency information as a pair, a data compression section for compressing data, and a sending section for sending compressed color information and transparency information to a receiving apparatus, and the telop image receiving apparatus has a reception and storage section for receiving and storing the information, a data decompression section for performing data decompression, an OA fill signal output section for ou
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: June 19, 2007
    Assignee: International Business Machines Corporation
    Inventors: Yasuhiro Kitabatake, Toshirob Hiromitsu, Yasushi Tsukamoto
  • Patent number: 7228351
    Abstract: A method and apparatus for managing contention among users for access to serialized resources in a system cluster containing multiple systems. Each user has an assigned need that is independent of contention of the user for a resource and may be either a holder or a waiter for a resource it is seeking to access. A local system stores local cluster data indicating a grouping of the resources into local clusters on the basis of contention on the local system and indicating for each local cluster the assigned need of a waiter for resources in the cluster. The local system receives remote cluster data from remote systems in the system cluster, which it combines with the local cluster data to generate composite cluster data. A holder on the local system of a resource in a composite cluster is managed in accordance with the composite cluster data for the cluster.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: June 5, 2007
    Assignee: International Business Machines Corporation
    Inventor: John E. Arwe
  • Patent number: 7216346
    Abstract: A method for managing the suspension and resumption of threads on an individual basis in an information handling system having an operating system (OS) kernel and a user process having multiple threads of execution. An originating thread issues a pthread_kill( ) service request to the OS kernel to send a specified signal (thread-stop or thread-continue) to a specified target thread within the same process to suspend or resume execution of the target thread. More particularly, in response to a request from a thread to suspend the execution of the target thread, the OS kernel sends a thread-stop signal (SIGTHSTOP) to the target thread, transferring control within the target thread from a normally executing program portion to a signal interrupt routine. Upon gaining control, the signal interrupt routine issues a service request to the kernel to stop the target thread.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: May 8, 2007
    Assignee: International Business Machines Corporation
    Inventors: Ernest S. Bender, Chun-Kwan K. Yee
  • Patent number: 7197585
    Abstract: A method and apparatus for managing the execution on guest processors of a broadcast instruction requiring a corresponding operation on other processors of a guest machine. Each of a plurality of processors on an information handling system is operable either as a host processor under the control of a host program executing on a host machine or as a guest processor under the control of a guest program executing on a guest machine. The guest machine is defined by the host program executing on the host machine and contains a plurality of such guest processors forming a guest multiprocessing configuration. A lock is defined for the guest machine containing an indication of whether it is being held by a host lock holder from the host program and a count of the number of processors holding the lock as guest lock holders. Upon decoding a broadcast instruction executing on a processor operating as a guest processor, the lock is tested to determine whether it is being held by a host lock holder.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: March 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jeffrey P. Kubala, Damian L. Osisek
  • Patent number: 7194616
    Abstract: According to the present invention a method and a device is provided for concurrent removal of processor capacity from a running computer. The method and device may, e.g., be used for non-disruptive removal of processors from the enabled physical configuration without any involvement of the operating system. The computer comprises a resource controller configured to control a physical resource pool including the actual physical resources and a capacity virtualizer configured to provide multiple sets of virtual resources from a capacity virtualizer resource pool, whereby the provided sets of virtual resources allow to host independent operating systems concurrently.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: March 20, 2007
    Assignee: International Business Machines Corporation
    Inventors: Christine Axnix, Klaus-Jurgen Kuebl, Andreas Muehlbach, Juergen Josef Probst, Carl J. Hollenback, Jeffrey P. Kubala
  • Patent number: 7188305
    Abstract: A method and apparatus for providing local data persistence for a Web server application. A Web page provided to a client application (e.g., a Web browser) by the server application contains a data entry area as well as a save button and a restore button. When the user actuates the save button, the Web page dynamically creates a new page that contains the data to be saved and a message prompting the user to save the new page in a user-designated location by using the file-saving function of the Web browser. The user may then close the original Web page, and the new page will remain saved locally. The user may then return to the original Web page and actuate the restore button to repopulate the original Web page with the data that has been saved locally. The save page contains a script function which becomes active when the page is loaded to perform the desired restoration function.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: March 6, 2007
    Assignee: International Business Machines Corporation
    Inventors: George E. Corbin, Joseph A. Kardash
  • Patent number: 7171591
    Abstract: An error correction code for encoding the presence of a special uncorrectable error as well as its type. In the encoder, modification logic modifies the regular data symbols to indicate the type of special uncorrectable error. The encoder appends to the regular data symbols a special uncorrectable error symbol indicating the presence of a special uncorrectable error to form an extended data word, which is encoded to generate a code word. In the decoder, a syndrome generator generates a syndrome vector using an assumed value for the special uncorrectable error symbol indicating the absence of a special uncorrectable error, while a syndrome decoder determines the presence of the special uncorrectable error by determining the presence of an error in the assumed value of the special uncorrectable error symbol. By so using its error detection logic, the decoder makes it unnecessary to actually store or transmit the special uncorrectable error symbol.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: January 30, 2007
    Assignee: International Business Machines Corporation
    Inventor: Chin-Long Chen
  • Patent number: 7096469
    Abstract: A method and apparatus for enforcing capacity limitations such as those imposed by software license agreements in an information handling system in which a physical machine is divided into a plurality of logical partitions, each of which is allocated a defined portion of processor resources by a logical partition manager. A software license manager specifies a maximum allowed consumption of processor resources by a program executing in one of the logical partitions. A workload manager also executing in the partition measures the actual consumption of processor resources by the logical partition over a specified averaging interval and compares it with the maximum allowed consumption. If the actual consumption exceeds the maximum allowed consumption, the workload manager calculates a capping pattern and interacts with the logical partition manager to cap the actual consumption of processor resources by the partition in accordance with the calculated capping pattern.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: August 22, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Kubala, Jeffrey M. Nick, Peter B. Yocom
  • Patent number: 7093183
    Abstract: Error correction and detection codes are designed with several properties: the ability to perform error correction and detection operations via syndrome generation in multiple cycles of information delivery from a source such as a set of memory chips; a code structure which is cooperatively designed in terms of the bits-per-chip architecture of a set of memory chips so as to provide enhanced robustness in the face of bus line and chip failures; and a structured parity check matrix which provides circuits which are cheaper, take up less room, and are faster than standard designs.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corporation
    Inventor: Chin-Long Chen
  • Patent number: 7093299
    Abstract: A system for authenticating digital data capable of preventing change or disguise of data by improvement or interchange in case of no confidentiality in the data itself so as to maintain the data. When writing digital data from an input device to a memory and transferring the digital data from the memory to a receiving device, device authentication is performed between the input device and the memory and between the memory and the receiving device respectively. At the same time, when writing digital data to the memory, in the case of implementing on the digital data an electronic signature by a one-way hash function and also reading from the memory and transferring the digital data, the implemented electronic signature is decrypted so as to transfer the digital data after ensuring that it has not been changed since it was recorded. Thus, it is possible to prevent change or disguise of data by improvement or interchange in case of no confidentiality in the data itself so as to maintain the data.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corporation
    Inventors: Koichi Kamijo, Norishige Morimoto, Akio Koide, Tohru Sakakura
  • Patent number: 7062660
    Abstract: A method and apparatus for controlling the performance of a mount operation changing the logical association of a first file system with a second file system of an information handling system by a user who may not have general authority to perform such a mount operation. In response to a request by a user to perform a requested mount operation on the first file system, a determination is made of whether the user has general authority to perform the requested mount operation, either because the user has general superuser authority or because the user has superuser authority for mount operations. If the user has general authority to perform the requested mount operation, the requested mount operation is performed. If the user does not have general authority to perform the requested mount operation, the requested mount operation is performed only if the user has a predetermined access authority to the first file system.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: June 13, 2006
    Assignee: International Business Machines Corporation
    Inventor: Joseph Quinlan
  • Patent number: 7062720
    Abstract: In order to avoid unnecessary and/or too shortly displayed wait window information occurring when a program is run on a highly performing hardware it is proposed to check whether a task which causes the display of the wait window information has completed after a predetermined first time interval after start of the task, and not to display the wait window information if the task has already completed within the first time interval, and otherwise display the wait window information at least during a predetermined second time interval, even if the task has already completed within the second time interval. Advantageously, the features can be implemented into an operating system. The advantage is that the flickering appearance of so-called wait windows is avoided.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: June 13, 2006
    Assignee: International Business Machines Corporation
    Inventors: Klaus Obermueller, Sebastian Wedeniwski
  • Patent number: 7039617
    Abstract: The present invention relates to electronic purse systems, and in particular it relates to the improved management of multiple money flows in such systems. According to the basic principles of the present invention it is proposed that the secure access modules (SAMs) of a purse provider support multiple user groups or environments in the system while still requiring only one system key. The user groups or environments are identified by a so-called float ID tag which is advantageously added to each set of data involved in a load or purchase process performed by the user of the electronic purse system.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: May 2, 2006
    Assignee: International Business Machines Corporation
    Inventors: Hartmut Droege, Martin Witzel
  • Patent number: 6985240
    Abstract: A method and apparatus for retrieving information about an object of interest to an observer. A position sensor wearable by the observer generates position information indicating the position of the observer relative to a fixed position. A direction sensor wearable by the observer generates direction information indicating the orientation of the observer relative to a fixed orientation. An object database stores position information and descriptive information for each of one or more objects. An identification and retrieval unit uses the position and direction information to identify from the object database an object being viewed by the observer by determining whether the object is along a line of sight of the observer and retrieves information about the object from the database. The identification and retrieval unit retrieves the descriptive information stored for the object in the database for presentation to the observer via an audio or video output device.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Oliver Benke, Boas Betzler, Thomas Lumpp, Eberhard Pasch
  • Patent number: 6983407
    Abstract: A plurality of pseudo random bit-pattern generators (PRPGs), advantageously linear feedback shift registers (LFSRs), having predetermined lengths and individual different tap locations for providing a respective sequence of pseudorandom bit-patterns. An output from a predetermined respective tap location at each LFSR is fed to a common OR-gate, a selected subset of the LFSRs are initialized with all bit storing locations to “0” in order to generate a respective permanent “0”-bit sequence, and the output of the OR-gate is used for reading the weighted or flat random bit output-pattern thereof. By controlling the number of zero-set LFSRs—a subset of the LFSRs—the weight of the generated output-pattern can be controlled.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: January 3, 2006
    Assignee: International Business Machines Corporation
    Inventors: Joerg Georg Appinger, Michael Juergen Kessler, Manfred Schmidt
  • Patent number: 6981165
    Abstract: A method and apparatus for handling an interrupt from a real-time clock to increment a program clock in a computer system while compensating for missed interrupts due to contention on a system bus from a DMA controller or the like. In accordance with the invention, a count is stored representing a cumulative interval of time that has elapsed without a corresponding incrementing of the program clock. In response to an interrupt from the real-time clock, the processor transfers control to an interrupt handling routine, which determines the interval of time that has elapsed since the previous real-time clock interrupt and increments the cumulative interval of time by the actual interval of time that has elapsed since the previous real-time clock interrupt.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: December 27, 2005
    Assignee: International Business Machines Corporation
    Inventor: Mark D. Marik
  • Patent number: 6981125
    Abstract: A method and apparatus for managing shared virtual storage in an information handling system in which each of a plurality of processes managed by an operating system has a virtual address space comprising a range of virtual addresses that are mapped to a corresponding set of real addresses representing addresses in real storage. The virtual address spaces are 64-bit address spaces requiring up to five levels of dynamic address translation (DAT) tables to map their virtual addresses to real addresses. One or more shared ranges of virtual addresses are defined that are mapped for each of a plurality of virtual address spaces to a common set of real addresses. The operating system manages these shared ranges using a system-level DAT table that reference a shared set of DAT tables used by the sharing address spaces for address translation, but is not attached to the hardware address translation facilities or used for address translation.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: December 27, 2005
    Assignee: International Business Machines Corporation
    Inventor: David B. Emmes
  • Patent number: 6976260
    Abstract: A single atomic instruction is used to change up to four disjoint areas in memory concurrently in an extended compare and swap operation, replacing traditional locks for serialization and providing recovery for all queue manipulations. Use count-based responsibility passing is employed so that any number of tasks can read the various message queue chains, concurrent with queue updates being made. A summary queue update sequence number is maintained to provide concurrent chain update detection, so that any number of tasks can add elements to the end, or remove elements from the middle (i.e. any where in the chain) concurrently. Concurrent footprinting is used with chain manipulation, so that all (or none) of the chaining indicators and a footprint are set with a single, non-interruptible instruction, making it possible for recovery to always take the correct action.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: December 13, 2005
    Assignee: International Business Machines Corporation
    Inventors: Donald F. Ault, David R. Cardall, Donald W. Schmidt
  • Patent number: 6971014
    Abstract: The invention relates to a device and a method for administering, in particular for creating and changing, identifying characteristics. During input of the new identifying characteristic by a user a check of the identifying characteristic is performed. Depending on the result of the check, a facility for termination of input of the new identifying characteristic is activated or deactivated as appropriate. The present invention substantially improves user-friendliness in the creation and changing of identifying characteristics, as failed attempts to input the new identifying characteristics are avoided.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: November 29, 2005
    Assignee: International Business Machines Corporation
    Inventors: Joachim Hagmeier, Michael Kaisser