Patents Represented by Attorney, Agent or Law Firm William A. Kinnaman, Jr.
  • Patent number: 7752262
    Abstract: A load balancing system and a corresponding computer-readable medium are proposed. The load balancing system is used in environments (e.g., implementing a licensing management application) wherein each client is associated with a preferred server storing specific information for the client. Each client periodically detects a workload and a response time of all the servers. The client selects a subset of nearest servers (according to their response times). The server in that subset with the lowest workload is set as an eligible server. Whenever a ratio between the workload of the preferred server and the workload of the eligible server exceeds a predefined threshold value (e.g., 1.1), the client switches to the eligible server (transferring the corresponding specific information). The system of the invention exhibits a slow dynamic, and tends to reach a steady condition (wherein the specific information of the clients is not continuously moved across the system).
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Domenico Di Giulio, Bruno Portaluri, Ricardo Rossi
  • Patent number: 7752585
    Abstract: Best and most recent NDR types are selected for all RLM's in a design in order to achieve timing closure. The selection employed uses two levels of filtering to examine the NDR types for each RLM, and based on the outcome of the filtering selects the most appropriate NDR type for input to the timing analysis. In one arrangement, the selection scheme is completely automated and is performed at the beginning of a timing analysis via script-driven processes.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Christopher M. Carney, Vern A. Victoria
  • Patent number: 7747726
    Abstract: A method and apparatus for obtaining a local performance measure for a particular server in a particular tier in a transaction environment in which transactions pass through multiple tiers with multiple servers at each tier. The contribution from the particular server to the total end-to-end response time for a set of transactions is scaled by the ratio of transactions passing through the particular tier to transactions passing through the particular server to obtain a scaled contribution from the particular tier. This is added to the contribution from outside the particular tier to obtain a modified total end-to-end response time from the perspective of the particular server. The modified total end-to-end response time is divided by the number of transactions in the set to obtain a modified average end-to-end response time from the perspective of the particular server, which is used to control allocation of resources to the server.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: June 29, 2010
    Assignee: International Business Machines Corporation
    Inventors: Mathew S. Thoennes, Peter B. Yocom
  • Patent number: 7734676
    Abstract: The invention relates to the control of servers which process client work requests in a computer system on the basis of resource consumption. Each server contains multiple server instances (also called “execution units”) which execute different client work requests in parallel. A workload manager determines the total number of server containers and server instances in order to achieve the goals of the work requests. The number of server instances started in each server container depends on the resource consumption of the server instances in each container and on the resource constraints, service goals and service goal achievements of the work units to be executed. At predetermined intervals during the execution of the work units the server instances are sampled to check whether they are active or inactive.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Greg M. Dritschler, Guenter Vater, Robert Vaupel, Peter B. Yocom
  • Patent number: 7734592
    Abstract: The present invention relates to a method for reducing a data repository with a plurality of sequentially ordered records. Each record is characterized by an identifier and comprises one or more data attributes and/or one or more links. The method includes the step of choosing a first record as base record and verifying whether the identifier of the sequentially next record can be generated from the base record by applying an identifier generating function. As a next step it is verified whether the data attributes and/or the links of the sequentially next record are identical with the data attributes and/or the links of the base record or can be generated from the base record by applying an attribute generating function and/or link generating function. If the above conditions are satisfied, a counter in the base record is incremented and the sequentially next record is deleted. The above steps are repeated for the subsequent records until the above conditions and are not satisfied for any record.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventor: Friedrich Beichter
  • Patent number: 7692480
    Abstract: A system to evaluate a voltage in a charge pump may include a transistor, and a transistor drain carried by the transistor with the transistor drain receiving a reference current. The system may also include a transistor gate carried by the transistor and connected to the transistor drain. The system may further include an additional transistor and an additional transistor gate carried by the additional transistor and connected to the transistor gate. The system may additionally include an additional transistor drain to receive the reference current mirrored from the additional transistor.
    Type: Grant
    Filed: July 6, 2008
    Date of Patent: April 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Fadi Hikmat Gebara, Jente Benedict Kuang, Paul D. Muench, Michael A. Sperling
  • Patent number: 7684533
    Abstract: A jitter measurement circuit and method having an input for receiving a reference signal whose jitter is to be measured, an input for receiving a clock signal having a series of cycles, and a measurement circuit for measuring the delay between the reference signal and the clock signal on a cycle by cycle bases, giving a cycle to cycle jitter measurement. The measurement circuit includes a plurality of n stages, each stage having a delay element including an input. The second and later delay elements have their inputs connected to the output of the previous stage and the first delay element has an input for receiving the reference signal. One of n latches is connected to the input of a corresponding one of the delay elements. Each latch has a clock input for receiving the clock signal, and an output for latching the value on the latches input when the clock input is clocked by an edge of the clock signal.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: March 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: James Eckhardt, Paul D. Muench, George E. Smith, III
  • Patent number: 7681169
    Abstract: A method for pre-wiring through multiple levels of metal using flues includes steps of: receiving information comprising flue geometries and flue properties; producing multiple routing patterns of a design for the flues; identifying macro instance terminals to be pre-wired in the design; selecting at least one of the routing patterns for the macro instance terminals in the design to avoid blockage; and instantiating the design such that the flues can be manipulated as vias.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: March 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Christopher J. Berry, Michael A. Bowen, Michael R. Scheuermann, Michael H. Wood
  • Patent number: 7676779
    Abstract: A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: March 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Reinaldo A. Bergamaschi, Sean M. Carey, Brian W. Curran, Prabhakar N. Kudva, Matthew E. Mariani, Mark D. Mayo, Ruchir Puri
  • Patent number: 7672997
    Abstract: A method, system, and program product for controlling the content displayed during a computer driven presentation of a presentation graphics application. Hidden object presentation properties are assigned to presentation graphics objects during creation of a presentation graphics file, the properties controlling the circumstances under which hidden objects are displayed during a computer driven presentation or screenshow. One type of hidden object presentation property indicates whether an object is viewable on an audience display and presenter display, or only a presenter display, during a multi-display screenshow. Another type of hidden object presentation property, such as hidden object value, determines the audience to which the object is displayed. Hidden object value properties may be hierarchical, individually selectable in any combination, or mutually exclusive.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: March 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ira L. Chavis, Lynn G. Winkelbauer
  • Patent number: 7665079
    Abstract: It is one object of the present invention to provide a program execution method for performing greater optimization. A program execution apparatus according to the present invention performs a transfer from an interpreter process to a compiled code process in the course of the execution of a method. At this time, if no problem occurs when a transfer point is moved to the top of a loop, the transfer point for code is so moved. And when a transfer point is located inside a loop, a point that post-dominates the top of the loop and the transfer point is copied to a position immediately preceding the loop. Then, information for generating recalculation code is provided for the transfer point, and a recalculation is performed.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: February 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Toshiaki Yasue, Kazunori Ogata, Kazuaki Ishizaki, Hideaki Komatsu
  • Patent number: 7627114
    Abstract: Modular reduction and modular multiplication for large numbers are required operations in public key cryptography. Moreover, efficient execution of these two operations is important to achieve high performance levels in cryptographic engines and processes. The present invention uses multiplication and addition instead of using division and subtraction to perform modular arithmetic. The present invention also achieves some of its advantages through processing which begins with the high order bits coupled with judicious observations pertaining to circumstances under which carry output signals from addition operations are generated. These carry output signals are used to provide corrections which thus enable the use of the higher order bits and the efficiencies that such use engenders. Additionally, unlike other methods, the present invention avoids the baggage of preprocessing and post processing operations.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: December 1, 2009
    Assignee: International Business Machines Corporation
    Inventor: Chin-Long Chen
  • Patent number: 7606060
    Abstract: An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: October 20, 2009
    Assignee: International Business Machines Corporation
    Inventors: Yuen H. Chan, William V. Huott, Donald W. Plass
  • Patent number: 7592851
    Abstract: A high performance, set associative, cache memory tag multiplexer provides wide output pulse width without impacting hold time by separating the evaluation and restore paths and using a wider clock in the restore path than in the evaluation path. A clock controls the evaluation of the input signals. Its leading edge (i.e., rising edge) turns on NR to allow evaluation, its trailing edge (falling edge) turns off NR to stop evaluation. At this point, when NR is shut off, the inputs can start changing to set up for the next cycle. Hence the hold time of the input is determined by the clock trailing edge.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: September 22, 2009
    Assignee: International Business Machines Corporation
    Inventors: Yuen H. Chan, Ann H. Chen, Antonio R. Pelella, Shie-ei Wang
  • Patent number: 7543373
    Abstract: A MCM system board uses a stiffener arrangement to enhance mechanical, thermo and electrical properties by incorporating an LGA compression connector in a computer system. The present designs of large scale computing systems (LSCS) in IBM use a MCM that is attached to a system board and held together by a stiffening frame. Due to the nature of the manufacturing of the system board, there can be significant gaps formed in the mounting area of the MCM between the board and the stiffener. A method is described that not only fills the void, it also, in addition promotes thermo conduction of excess heat away from the MCM and at the same time promotes enhanced electrical properties of the LGA connections of the MCM to the system board.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: June 9, 2009
    Assignee: International Business Machines Corporation
    Inventors: Michael F. McAllister, Harald Pross, Gerhard H. Ruehle, Wolfgang A. Scholz, Gerhard Schoor
  • Patent number: 7529824
    Abstract: A method and apparatus for invoking a service in a service-oriented architecture in which a client invokes such service from a service provider using a selected transport binding. A service binding for a service invocation from the service provider is first negotiated in a negotiation process using a first transport binding. The service invocation is then handled using the service binding negotiated in the negotiation process. A client may first determine whether a server is capable of negotiating a service binding. If the server is capable of negotiating a service binding, the client negotiates a service binding with the server. Otherwise, a service binding is selected on the basis on diagnostic information available to the client without negotiating with the server. Separate service bindings may be negotiated for each of several portions of a communication path, either by the client and service provider or by intermediaries along the communication path.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: May 5, 2009
    Assignee: International Business Machines Corporation
    Inventor: Joshy Joseph
  • Patent number: 7487425
    Abstract: Byte or symbol organized linear block codes are optimized in terms of reducing the number of ones in their parity check matrices by means of symbol column transformations carried out by multiplication by non-singular matrices. Each optimized symbol column preferably, and probably necessarily, includes a submatrix which is the identity matrix which contributes to low weight check matrices and also to simplified decoding procedures and apparatus. Since circuit cost and layout area are proportional to the number of Exclusive-OR gates which is determined by the number of ones in the check matrix, it is seen that the reduction procedures carried out in accordance with the present invention solve significant problems that are particularly applicable in the utilization of byte organized semiconductor memory systems. Reduced weight coding systems are also generated in accordance with weight reducing procedures used in conjunction with modified Reed Solomon codes.
    Type: Grant
    Filed: May 17, 1993
    Date of Patent: February 3, 2009
    Assignee: International Business Machines Corporation
    Inventor: Chin-Long Chen
  • Patent number: 7484896
    Abstract: A conductive, compliant, deformable boot for a fiber optic or other cable assembly is described, which both provides traditional cable strain relief functions and extends over the body of the connector to form an electrically conductive shield over the cable receptacle aperture when the cable assembly is plugged into the aperture. The boot deforms slightly upon insertion of the cable assembly and compresses against a mating component to form a shield against electrostatic discharge which can accumulate on the cable or card and also to shield against electromagnetic emissions entering or leaving the circuit card package. The boot also shields against emissions when two cable assemblies are mated together by deforming slightly upon mating and then returning to its original state when the assemblies are disconnected.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: February 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Casimer M. DeCusatis, John H. Quick
  • Patent number: 7483536
    Abstract: To provide a method and a system for creating a mini time key from a time key, a plurality of mini time keys are created within a unit time period. First, a unit time decryption key is prepared immediately after the unit time is created. Then, the last mini time key is created by applying a one-way function to the unit time decryption key. A desired mini time key is created by applying the one-way function to a mini time key following the desired mini time key. In other words, the mini time keys are created as a timed series arranged in a descending order beginning with the last mini time key. In this manner, even when a specific mini time key is externally leaked for a specific reason, a following mini time key in a timed series can not be created by using this mini time key. In addition, even when the mini time keys are sequentially published, the security of the unit time decryption key is maintained.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: January 27, 2009
    Assignee: International Business Machines Corporation
    Inventor: Michiharu Kudo
  • Patent number: 7475108
    Abstract: A load balancing method and a corresponding system are proposed. The load balancing method is used in environments (e.g., implementing a licensing management application) wherein each client is associated with a preferred server storing specific information for the client. Each client periodically detects a workload and a response time of all the servers. The client selects a subset of nearest servers (according to their response times). The server in that subset with the lowest workload is set as an eligible server. Whenever a ratio between the workload of the preferred server and the workload of the eligible server exceeds a predefined threshold value (e.g., 1.1), the client switches to the eligible server (transferring the corresponding specific information). The method of the invention exhibits a slow dynamic, and tends to reach a steady condition (wherein the specific information of the clients is not continuously moved across the system).
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: January 6, 2009
    Assignee: International Business Machines Corporation
    Inventors: Domenico Di Giulio, Bruno Portaluri, Ricardo Rossi