Abstract: Apparatus for testing dynamic noise immunity of digital integrated circuits wherein noise pulses of predetermined duration and amplitude are applied to the inputs of an integrated circuit under test. The tested circuit outputs which normally are at logic level 0 are connected to the inputs of a first group of control logic gates, while the tested circuit outputs which normally are at logic level 1 are connected to the inputs of a second group of control logic gates. The outputs of such groups feed a fault detection circuit. The input voltage thresholds of control logic gates is adjusted by suitable circuits so as to check the dynamic noise immunity of the integrated circuit under test for a predetermined logic swing.

Abstract: A continuous form for a printer, suitable for office automation, consists of: (A) a plurality of contiguous sheets identified by reference marks regularly spaced along the form length having sheets of a first type with a preprinted heading being followed at a preestablished frequency in the form by sheets of a second type, without such preprinted heading, so that, when used in a printer provided with a cutter, by printing on selected sheets of the form and by cutting the printed sheets from the form and by collecting the printed sheets, letters, circulars and similar paper on several sheets of equal size and different type can be automatically obtained, or (B) in an alternative embodiment, a plurality of identical contiguous sheets each comprising a preprinted head zone and a tail zone, both zones having the same height, the length of the sheets exceeding a desired final sheet length by the height of the tail zone, so that letters, circulars and similar papers on several sheets of equal size and different typ

Abstract: A document holder attachable to a display terminal used to support one or more documents to be referenced by the display terminal user when information is entered or displayed on the display terminal screen is disclosed. The document holder is supported by an easel bracket which fits in an annular groove in the display terminal cover. The document easel is attached to the easel bracket such that an adjustment in the swivel or tilt of the display terminal for operator viewing convenience also results in a corresponding adjustment in the document holder such that the document holder always remains in the same relative viewing position with respect to the display terminal screen. The document holder can be easily added or removed from the display terminal and is reversible for either righthanded or lefthanded use.

Abstract: One or more common buses are provided for coupling a plurality of units in a data processing system for transfer of information therebetween. The central processing unit (CPU) allocates the one or more common buses to one of the requesting units as a function of request type and on which of one or more common buses the requesting unit is located. Bus requests are generated in a synchronous manner by use of a timing signal originating in the CPU which is connected in series between the one or more units on each of the one or more common buses.

Abstract: Apparatus and method for performing a logical not function in a multi-compare environment is disclosed. By performing two equivalence compares of a measured variable against selectable target values and using the result of the equivalence compares to selectivity set or reset a bistable element, the need for inverting and multiplexing the output of a comparator that is otherwise required when performing a NOT equivalence function in a single-compare environment is eliminated. The not function logic is used in a system analyzer connected to a data processing system and is used to selectively enable the tracing of software execution as a function of whether or not a variable is a predefined value.

Abstract: A technique and apparatus for storing data and addressing stored data in a memory from which multiple words of data are to be retrieved in parallel is disclosed. The memory is addressed by providing the address of the first of N consecutive words to be retrieved in parallel. The data is stored in memory in physical data words which contain N logical data words such that the addressing of one physical data word will result in N logical data words being read in parallel from the memory. Each physical data word contains the contents of the logical data word having the same address as that of the physical data word in its leftmost position followed in the next right position by the contents of the logical data word having the next higher address, and so on until the rightmost position of the physical data word contains the contents of the logical data word with an address equal to the physical data word address plus N-1.

Abstract: A clock system for providing rectangular wave forms or wave trains, with each wave train having a selectable predetermined clock cycle period. A rectangular wave train is generated by a generator comprising a first delay line coupled to an inverter by using a multitapped second delay line to delay the rectangular wave train by selectable predetermined period. A control signal is formed which when fed into the generator produces a second rectangular wave train with a clock cycle period equal to the rectangular wave train clock cycle period plus the period of the second selected predetermined delay. By serially connecting a multitapped third delay line in series with the second delay line and by providing a first switch to select one of the outputs from said third delay line, the clock cycle period of the clock system may be adjusted.

Abstract: In a data processing system which includes a central processing unit and one or more main memory units comprised of semiconductor dynamic random access memory chips, logic is provided within the system to provide for the single stepping of the central processing unit clock thereby allowing for the execution of one CPU cycle. The system logic is organized such that the memory refresh command signals, which are normally generated by the CPU, are generated by the single step logic thereby maintaining the contents of the main memory modules. The logic of the overall data processing system is organized such that most transfers of information between the main memory, the CPU and I/O controllers, to which peripheral devices are connected, may take place in the single step mode of operation without the loss of information.

Abstract: In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. In order to allow a data entry operator inputting data via a peripheral device connected to an IOC the ability to correct errors, a backspace character is provided so that the operator can enter it to indicate to the system to ignore the preceding character.

Abstract: An article of furniture used to support a computer terminal or a similar object having means to continuously adjust in a stepless fashion the table top height through the operation of a single operating lever located just beneath the table top which can be operated from a seated or standing position. Swinging the operating lever in one direction in the horizontal plane releases an adjustable length gas spring controlling table top height, allowing for the raising or lowering of the table top which is followed by the return of the operating lever to its original position which locks gas spring at its new length and rigidly locks the table top at its adjusted height.

Abstract: A refresh memory address generation apparatus for a video display controller is disclosed wherein rows of character information stored in a display refresh memory may be relocated without requiring the reconstruction of the display information as stored in the display refresh memory. A roll register and PROMs precoded to perform modular addition and multiplication are used to generate an address used to access the display controller refresh memory such that all but one stationary row of information on the display screen may be scrolled (rolled) up. The scrolling of the information on the display screen is accomplished without requiring movement of the display information in the refresh memory, and the only rewrite of information in the refresh memory is done to blank the one row of information which is vacated.

Abstract: A strobe generator in a data entry input device is responsive to an input strobe signal from a keyboard system to generate a strobe signal which is not affected by electrical noise produced by electrostatically or electromagnetically induced signals in the signal lines running between the keyboard system and the data entry device input logic. An accurate output strobe signal is generated by utilizing a retriggerable logic circuit to filter out noise signals of a duration shorter than a predetermined period. The predetermined period is chosen to be less than the minimum duration of a valid input strobe signal and greater than the duration of active noise signals. The strobe generator retains the output strobe signal in the active state by use of a flip-flop until the strobe generator receives a reset signal acknowledging that the output strobe signal has been sampled by the data entry device input logic.

Abstract: A quick disconnect male terminal is disclosed having a stem which is inserted into a circular hole in the printed circuit board prior to wave soldering the terminal to the printed circuit board. The terminal is designed to use minimal material, to use little surface area on the printed circuit board, and be easily assembled into printed circuit boards. The terminal stem is embossed with a V-shape to increase its strength and to increase the solder wicking action through the hole in the printed circuit board. The tip of the V-shaped terminal stem protruding through the hole in a printed circuit board may also be flattened as a means of affixing the terminal prior to wave soldering.

Abstract: A method for determining whether test probes of a test fixture on an automatic test equipment (ATE) device are in contact with the intended test points on an electronic assembly under test. The undetected failure of the test probes to contact the test points on the electronic assembly test, such as a printed circuit board can result in meaningless test results or lead to unnecessary further testing or replacement of nonfaulty components that tested as failed. The method is directed to detecting which test probes are not in contact with their corresponding test points on the electronic assembly undergoing test by ATE.

Abstract: An apparatus and method for determining whether test probes of a test fixture on an automatic test equipment (ATE) device are in contact with the intended test points on an electronic assembly under test. The undetected failure of the test probes to contact the test points on the electronic assembly test, such as a printed circuit board can result in meaningless test results or lead to unnecessary further testing or replacement of nonfaulty components that tested as failed. The apparatus and method are directed to detecting which test probes are not in contact with their corresponding test points on the electronic assembly undergoing test by ATE.

Abstract: In a data processing system which includes a central processing unit (CPU) having one or more common buses to which one or more main memory units for storing program software instructions and program data are connected, logic is provided within the CPU for detecting an attempt to access a main memory location not contained in the one or more main memory units present in the data processing system. Logic is provided for detecting the attempt to access the nonexistent memory location for the case where the access was being done in the course of the CPU executing a software instruction or for the case of where the access was being done to transfer data between the main memory and an input/output controller connected to one of the one or more common buses.

Abstract: A data processing system remote monitor interface includes a first device which transmits different types of time-related information signals along multiple parallel channels to a second device for reception and combination into a different number of information signal outputs. The different types of digital information signals are synchronized by the first device prior to transmission to the second device. Components in the first device, the multiple parallel channels, and the second device are selected to maintain signal synchronization by minimizing signal skew thereby eliminating the necessity for signal resynchronization in the second device. The second device includes a receiver section which has a plurality of receivers. Each receiver operates to receive only one digital information signal and to pass the received signal onto its output.