Abstract: A printed circuit card enclosure is disclosed having end plates and shelf members which are secured together to form the enclosure. The shelf members are provided with holes for receiving flexible snap-in card guides which are used to retain and support printed cards within the enclosure. The shelf members and card guides are further designed such that in a card enclosure designed to retain multi-levels of printed circuit cards, a single shelf member may be shared between two adjacent levels of printed circuit cards and the card guides installed within a single set of holes with the upper card guide being used to retain the lower edges of printed circuit cards in the upper level and the lower card guides being used to retain the upper edges of printed circuit cards in the adjacent lower level.

Abstract: In a data processing system which includes a central processing unit (CPU), main memory and a plurality of input/output controllers (IOCs) connected to a common bus information can be transferred between the main memory and CPU and main memory and the IOCs. Logic is provided within the CPU to align a byte of data on the data lines of the common bus such that it can be taken from the data lines by the main memory and written into a multi byte word without further alignment. Logic is provided within the CPU to extract from a multi byte word of data read from main memory and appearing on the common bus data lines the appropriate byte of data and to align it on the common bus data lines such that an IOC may pass the data byte to a peripheral device without further alignment.

Abstract: In a data processing system which includes a central processing unit and one or more main memory units for storing program software instructions and program data, logic is provided within the CPU to signal the main memory units, comprised of semiconductor random access memory chips, that a memory refresh operation can be performed. The logic is organized such that the memory refresh operation signal may be given to the main memory units in parallel with and without detracting from other CPU operations. Further, logic is provided within the CPU to interrupt the CPU normal processing and perform a memory refresh operation if one has not been performed with a predetermined time period. Logic is provided within each main memory unit to accept the memory refresh signals from the CPU and to discard those memory refresh signals that would refresh the memory more frequently than required to retain the memory contents thus reducing main memory power consumption.

Abstract: In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of information, blocks of information may be transferred between main memory and an input/output controller (IOC) synchronously with operations of the central processor unit (CPU). Logic is provided for enabling one unit of the block of information to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the CPU for determining: the direction of the data transfer, the address of the location of the unit of data to be transferred to/from the main memory, and the number of units of data remaining to be transferred between the main memory and the IOC.

Abstract: Multiple common buses are provided for coupling a plurality of units in a data processing system for the transfer of information therebetween. The central processing unit (CPU) allocates the multiple common buses to one of the units in response to bus requests received from various units desiring to use the common buses. Bus requests are generated in a synchronous manner by use of a timing signal originating in the CPU which is connected in series between the one or more units on each of the multiple common buses.

Abstract: In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processing unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Direct Memory Access (DMA) data transfer operation in which the requesting IOC requests a DMA data transfer of the CPU. Means are provided within the system for: resolving conflicting requests for the one or more common buses, the CPU to acknowledge the DMA request, the IOC to transfer the address of the location where the unit of data is to be written into main memory followed by the unit of data, or the IOC to transfer the address of the location in main memory from which the unit of data is to be read and then receive the unit of data read from main memory.

Abstract: In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the system for: resolvng conflicting requests for the one or more common buses, the CPU to acknowledge the DMC request, identifying the requesting IOC to the CPU, accessing one unit of data from main memory or the IOC, and transferring the unit of data to the IOC or main memory.

Abstract: In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a first unit, such as a central processor, to make a multiple fetch request of a second unit, such as a memory, during a first transfer cycle. The multiple fetch request requests the second unit to transfer multiple parts of data to the first unit during multiple further transfer cycles, wherein one part of data is transferred in each further transfer cycle. Logic is provided in the second unit to enable the second unit to indicate to the first unit, except during the last further transfer cycle, that each further transfer cycle will be followed by another further transfer cycle.

Abstract: A clock system for providing rectangular wave forms or wave trains, with each wave train having a selectable predetermined clock cycle period. A rectangular wave train is generated by a generator comprising a delay line coupled to an INVERTER. By using a second delay line to delay the rectangular wave by a selectable predetermined delay period, a control signal is formed which when fed into the generator produces a second rectangular wave train with a clock cycle period equal to that of the rectangular wave clock cycle period plus the period of the second predetermined delay. The addition of a synchronization circuit permits the clock cycle period to be dynamically selected during a clock cycle. This provides a rectangular train with the period of each clock cycle being any of the predetermined clock cycle periods independent of the clock cycle period of preceding or succeeding clock cycles.

Abstract: In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority requesting unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a multiple fetch operation in which the master unit requesting multiple words of information from the slave unit during a first bus transfer cycle may receive such information from the slave unit during a series of later slave generated bus cycles. Logic is provided for enabling any other units to communicate over the common bus during the time between the first cycle and such last cycle during which the slave unit responds, thereby enabling at least two pairs of units to communicate with each other respectively, in an interleaved manner.

Abstract: A final effective address of an operand is generated in a microprogrammed data processing system by use of a base address register which may include an unindexed address, an index register which may include an indexed address value, an instruction register which may include an instruction word, which instruction word provides control over the addressing of a control store dependent upon the state of a selected one of a plurality of test conditions. One of the test conditions indicating whether some of the addressing values used in the generation of the effective address are in a short address format or in a long address format. The address control store word provides signals for controlling the operation of the system, including the branch in between such major operations as instruction fetching, addressing, reading, writing, and execution as well as branching between minor operations which are included in the major operations.

Abstract: A display device includes improved raster scan apparatus which provides for the video display of information in timed synchronization with cycles of AC power. The raster scan apparatus includes a circuit which monitors the periodicity of the AC input power to the display device. This circuit is operative to initialize certain raster scan logic which thereafter authorizes the next raster scan sweep. In this manner, each raster scan is synchronized with respect to the cyclical AC power. This synchronization eliminates visible distortion on the video output of the display device.

Abstract: In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred during asynchronously generated information transfer cycles. Logic is provided for enabling a first unit to transfer first information to a second unit during a first request transfer cycle requesting that the second unit transfer second information to the first unit during a later first response transfer cycle. Logic is also provided to enable the first unit to transfer third information to a third unit during a second request transfer cycle requesting that the third unit transfer fourth information to the first unit during a later second response transfer cycle. Logic is provided that enable the first unit to transfer the third information before receiving the second information and logic is further provided that enables the first unit to receive the second information before or after receiving the fourth information.