Abstract: An apparatus for managing vertical dependencies between instructions in first and second instruction pipelines includes: 1) identifier (ID) reclaim circuitry for determining a sequential set of retired identifiers associated with retired instructions and for determining a next retire ID sequentially following the set; 2) first ID generation circuitry for sequentially assigning identifiers to destination registers associated with instructions entering the pipelines; 3) second ID generation circuitry associated with the first pipeline for identifying a first dependent source register associated with a first dependent source operand of a first instruction entering the first pipeline and assigning an ID of the first register to the first operand; and 4) instruction scheduling circuitry for comparing the first operand ID of the first instruction with the next retire ID and scheduling the first instruction for execution if the first operand ID is less than or equal to the next retire ID.

Abstract: Metal taps for bus conductors are formed within an active layer, within one or more of the metallization levels, on the active side of a substrate in the area of a bus via. Alignment marks are formed in the same metallization level, in the same area. A slot is then blind etched from the backside of the substrate, exposing the metal taps and the alignment marks. The slot is etched, using an oxide or nitride hard mask, into the backside surface of the substrate with significantly sloped sidewalls, allowing metal to be deposited and patterned on the backside. An insulating layer and deposited metal on the backside surface of the substrate may require a blind etch to expose alignment marks, if any, but front-to-back alignment precision utilizing the exposed alignment marks may permit much smaller design rules for both the metal tabs and the backside interconnects formed from the metal layer. Backside contact pads may also be formed from the metal layer.

Abstract: A structure and method for creating a contact between a conductive layer and a pad for dissipating electrostatic charges comprising the steps of, forming a pad and a composite insulating layer between and over conductive plates on a substrate, wherein the insulating layer isolates and protects the conductive plates and pad from damage, the insulating layer comprising a dielectric region underlying a conductive layer. A passivation layer is formed over at least a portion of the conductive layer and a photoresist is patterned over at least a portion of the passivation. An opening is etched through the passivation and the insulating layers, wherein the photoresist and the conductive layer serve as masks. Finally, a conductive material is deposited in the opening to form an electrical contact between the pad and the conductive layer.

Abstract: A data processing system having a distributed reservation station is provided which stores basic blocks of code in the form of microprocessor instructions. The present invention is capable of distributing basic blocks of code to the various distributed reservation stations. Due to the smaller number of entries in the distributed reservation stations, the look up time required to find a particular instruction is much less than in a centralized reservation station. Additional instruction level parallelism is achieved by maintaining single basic blocks of code in the distributed reservation stations. With a distributed reservation station, an independent scheduler can be used for each one of the distributed reservation stations. When the instruction is ready for execution, the scheduler will remove that instruction from the distributed reservation station and queue that instruction(s) for immediate execution at the particular execution unit.

Abstract: There is disclosed a voltage controlled oscillator (VCO) that receives +V(IN) and −V(IN) control voltages and outputs a VCO output signal having an oscillation frequency determined by the +V(IN) and −V(IN) control voltages. The VCO comprises: 1) a storage capacitor charged linearly by a constant charge current and discharged linearly by a constant discharge current; 2) a comparator for comparing the storage capacitor voltage to an upper threshold voltage and a lower threshold voltage. The comparator output drops to a negative saturation voltage (−V(SAT)) when the storage capacitor voltage rises above the upper threshold voltage and rises to a positive saturation voltage (+V(SAT)) when the storage capacitor voltage drops below the lower threshold voltage.

Abstract: There is disclosed a circuit for determining the number of Logic 1 bits in a group of N data bits.

Abstract: A preformed adhesive layer for joining components within integrated circuit packaging includes venting slots for controlling the size and location of voids within an assembled integrated circuit package. Air randomly entrapped between the surfaces of the adhesive layer and adjoining components during assembly will generally release into the venting slots during subsequent assembly and/or mounting steps performed at elevated temperatures, rather than creating internal pressures causing separation of package components or releasing into the encapsulant. Die delamination and encapsulant void problems occurring during reflow or other assembly and mounting processes as a result of entrapped air are avoided.

Abstract: An integrated circuit (IC) device comprising: 1) an integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and sidewalls extending between the first surface and the second surface; and 2) an integrated circuit (IC) package for supporting the IC die, wherein the IC package is attached to at least one of the sidewalls of the IC die such that at least a portion of the IC die first surface and at least a portion of the IC die second surface are exposed.

Abstract: A cache flush controller, and an associated method, selectably flushes a memory cache of a data processor. The cache flush controller operates at a memory bus level of the data processor and operates to flush a selected line, or lines of the memory cache by writing arbitrary, selected values to the selected line or lines of the memory cache.

Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.

Abstract: A Central Processing Unit (CPU) hotpatch circuit compares the run-time instruction stream against an internal cache. The internal cache stores embedded memory addresses with associated control flags, executable instruction codes, and tag information. In the event that a comparison against the current program counter succeeds, then execution is altered as required per the control flags. If no comparison match is made, then execution of the instruction that was accessed by the program counter is executed.

Abstract: A method for exposed die molding for integrated circuit packaging is provided that includes providing a mold comprising an upper mold with a flexible material, a lower mold, and a floating plunger. A substrate of an integrated circuit structure is clamped between the upper mold and the lower mold. An integrated circuit die of the integrated circuit structure is clamped between the floating plunger and the upper mold through the flexible material.

Abstract: A structure and method is disclosed for dissipating electrostatic charges comprising an insulating layer between and over a plurality of conductive plates, wherein the insulating layer isolates the conductive plates and protects the conductive plates from damage, and wherein the insulating layer comprises a conductive discharge grid adjacent the conductive plates.

Abstract: The present invention utilizes a “virtual” condition code (VCC) which can control the instruction sequence in a microprocessor. The virtual condition code is stored in an internal, non-architected register that is not visible to the programmer, but is used by various microprocessor instructions to determine when a branch is to be taken. For example, the virtual condition code can be used as a condition for branching out of a series of repetitive instructions. The virtual condition code (VCC) can eliminate a portion of the processing overhead used when determining whether a sequential number, such as a count value in a register associated with a repetitive instruction, e.g. a LOOP, is zero. In accordance with one aspect of the present invention, a LOOP instruction will decrement a count value in a register (to maintain compatibility with the ISA).

Abstract: There is disclosed a field programmable gate array for use in an integrated processing system capable of testing other embedded circuit components in the integrated processing system. The field programmable gate array detects a trigger signal (such as a power reset) in the integrated processing system. In response to the trigger signal, the field programmable gate array receives first test program instructions from a first external source and executes the first test program instructions in order to test the other embedded circuit components in the integrated processing system. When testing of the other embedded circuit components is complete, the field programmable gate array loads its normal operating code and performs its normal functions.

Abstract: There is disclosed, for use in a digital signal processor, an apparatus for dynamically sizing a hardware loop that executes a plurality of instruction sequences forming a plurality of instruction loops. The apparatus comprises: 1) N pairs of loop start registers and loop end registers, each loop start register for storing a loop start address and each loop end register for storing a loop end address; 2) N comparators, each of the N comparators associated with one of the N pairs of loop start registers and loop end registers, wherein each of the N comparators compares a selected one of a first loop start address and a first loop end address to a fetch program counter value to detect one of a loop start hit and a loop end hit; and 3) fetch address generation circuitry for detecting the loop start hit and the loop end hit and fetching from an address in a program memory an instruction associated with one of the loop start hit and the loop end hit and loading the fetched instruction into the hardware loop.

Abstract: A system and method is provided to reduce the latency associated with saving and restoring the state of the floating point registers in a microprocessor when switching tasks between floating point and MMX operations, or between tasks within the same context. The present invention maintains a secondary register file along with the primary floating point register file in the CPU. The primary register will keep the state of the floating point task “as is” upon the occurrence of a task switch to MMX, or another context. The address of the area where the FPU state is saved is maintained in a save area address register. The secondary register is then utilized by the other context to store intermediate results of executed instructions. In the majority of cases when a context switch back to floating point operations occurs, the previous state is restored from the primary register without incurring the latency of retrieving the instructions and data from the memory subsystem.

Abstract: Within a capacitive fingerprint detection device, finger detection is provided by a plurality of resistive grids overlying the fingerprint sensor electrodes to measure the resistance of the finger placed on the sensor surface. A finger placed on the sensor surface connects the resistive rids and allows the skin resistivity to be measured. The measured resistance is compared to a reference resistance or range of resistances to determine whether the measured resistance matches the expected bio-characteristics of living skin tissue. The finger detection thus provides anti-spoofing protection for the fingerprint detection device.

Abstract: There is disclosed a circuit for determining if an N-bit number is equal to a power of two. The circuit comprises: 1) a first stage of detection gates, each of the first stage detection gates capable of receiving a first data bit and a second data bit from the N-bit number and generating a first output bit and a second output bit, wherein the first and second output bits are 01 if the first and second data bits are different and are one of 00 and 11 if the first and second data bits are the same; and 2) a second stage of detection gates coupled to the outputs of the first stage of detection gates, each of the second stage detection gates receiving three of the first stage output bits and generating a first output bit and a second output bit, wherein the first and second output bits of the second stage detection gates are 01 if only one of the three first stage output bits is equal to Logic 1 and are one of 00 and 11 otherwise.

Abstract: A linear interpolation operator for determining the value y of a function of x when one knows the value y1 corresponding to x1, and a value y2 corresponding to x2 (where x2<x≧x1), comprises a first calculation circuit which determines the equation (xm+xM)/2; a second calculation which determines the equation (ym+yM)/2; a comparison circuit which compares x with (xm+xM)/2 so as to determine which one of the intervals [xm,(xm+xM)2], [(xm+xM)/2, xM] contains x and to feed back the limits of the selected interval into the first calculation circuit and the limits of the interval corresponding in y into the second calculation circuit.