Abstract: An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.

Abstract: Current drawn by the fingerprint sensor subject to electrostatic discharge events not fully dissipated by a pad ring is monitored. Upon detection of an overcurrent (e.g., an increase in the current drawn by approximately an order of magnitude) indicating that a latchup condition has occurred, power is removed from the sensor, together with all inputs to the sensor, until the latchup condition is cleared. If a processor or controller is employed by the sensor, the processor or controller is concurrently reset since a firmware crash may be induced by the latchup condition. If a parallel port or other communications connection is employed by the sensor, the overcurrent signal is employed to directly disconnect power and input signals to the sensor.

Abstract: A narrow array capacitive semiconductor fingerprint detection system includes an array of capacitive sensing elements. The array has a first dimension about the width of a fingerprint and second dimension less than the length of a fingerprint. A scan control unit is coupled to scan the array at a scan rate determined by the speed of finger movement over the array. The scan control unit scans the array capture partial fingerprint images. Output logic is coupled to the array to assemble the captured fingerprint images into a complete image based upon the direction of finger movement over the array. A mouse device is positioned adjacent the array in the path of finger movement over the array. The mouse device is coupled to provide finger movement speed information to the scan control unit. The mouse device is also coupled to provide finger movement direction information to the output logic.

Abstract: A narrow array optical fingerprint detector that substantially eliminates over-sampling of the array measures the speed of a finger moving over the array and scans the array at a rate determined by the speed of movement of the finger. The fingerprint detector measures the speed of finger movement with a transparent cylinder rotatably mounted adjacent the array. The transparent cylinder is mounted to engage the finger and rotate as the finger is swept past the array. A light chopper is mounted for rotation with the cylinder. A photo-sensor is mounted adjacent the light chopper. The photo-sensor produces a signal in response to light being chopped by the light chopper. The photo-sensor is operably connected to scanning circuitry. Each time the scanning circuitry receives a signal from the photo-sensor, the scanning circuitry scans the array.

Abstract: A method for fabricating interlevel contacts in semiconductor integrated circuits provides for formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

Abstract: Passivation for capacitive sensor circuits, which overlies the capacitive sensor electrodes and is normally conformal to the electrodes and the underlying interlevel dielectric, is planarized by forming a layer of flowable oxide over the electrodes before forming the passivation. The flowable oxide, which is preferably very thin over the electrodes to minimize loss of sensitivity, provides a substantially planar upper surface, so that passivation formed on the flowable oxide is also substantially planar. Alternatively, a deposited oxide planarized by chemical mechanical polishing may be employed to planarize the surface on which a passivation stack is formed. The planarized passivation provides markedly improved scratch resistance.

Abstract: A system and method is disclosed for providing mechanical planarization of a sequential build up substrate for an integrated circuit package. A planarization plate is placed in contact with an uneven external surface of a dielectric layer that covers underlying functional circuit elements and filler circuit elements. A heating element in the planarization plate flattens protruding portions of the external surface of the dielectric layer to create a flat external surface on the dielectric layer. After the flat external surface of the dielectric layer has cooled, it is then covered with a metal conductor layer. The method of the present invention increases the number of sequential build up layers that may be placed on a sequential build up substrate.

Abstract: The invention relates to monitoring error conditions in an integrated circuit. The integrated circuit has a packet router to which a plurality of functional modules are connected between which packets are transmitted. Each functional module is associated with an error monitoring register for monitoring error conditions. The error monitoring register contains a plurality of error flags which can be set when a particular error condition is detected. The invention particularly but not exclusively relates to the setting of communication error flags relating to errors in communication of the packet.

Abstract: A power management unit monitors current drawn by a fingerprint sensor circuit and generates a “heartbeat” signal during normal operation. If a latchup event occurs, with attendant increase in current drawn by the fingerprint sensor circuitry, the heartbeat signal terminates and an interrupt is subsequently triggered to start a latchup recovery routine. Power to the fingerprint sensor circuitry is switched off and the interrupt is then cleared by writing appropriate values to control bits within the power management register.

Abstract: A stable, process independent RC time constant for precision frequency response in automatic tuning is generated using a feedback loop employing a voltage controlled resistor to force current through the output node to equal a reference current. The only terms in the expression for the time constant affected by process variations are two resistances, which are uniformly affected by any process variations to maintain proportion. The open loop transfer function for the feedback loop contains only one pole; because no phase-locked loop or other complex circuit introducing multiple poles within the feedback loop are employed, the time constant tuning filter is intrinsically stable.

Abstract: A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner silicides with less likelihood of delamination or metal oxidation may thus be formed.

Abstract: The invention provides a method and system for computing transcendental functions quickly: (1) the multiply ALU is enhanced to add a term to the product, (2) rounding operations for intermediate multiplies are skipped, and (3) the Taylor series is separated into two partial series which are performed in parallel. Transcendental functions with ten terms (e.g., SIN or COS), are thus performed in about ten clock times.

Abstract: The invention provides a method and apparatus for optimizing instruction prefetch and caching in a processor. In the preferred embodiment, a path prediction circuit maintains information about which cache lines are likely to be executed in the future. This information is used to independently fetch the predicted cache lines, store them in a prefetch queue, and load them in to the instruction cache as instructions contained in these lines are about to be decoded by the processor. A plurality of cache lines can be in the process of being simultaneously fetched from main memory to load the prefetch queue.

Abstract: A method is provided for forming an improved contact opening of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Planarization of the semiconductor structure is maximized and misalignment of contact openings is tolerated by first forming a conductive structure over a portion of a first body. A thin dielectric layer is formed at least partially over the conductive structure. A thick film, having a high etch selectivity to the thin dielectric layer, is formed over the dielectric layer. The thick film is patterned and etched to form a stack substantially over the conductive structure. An insulation layer is formed over the thin dielectric layer and the stack wherein the stack has a relatively high etch selectivity to the insulation layer. The insulation layer is etched back to expose an upper surface of the stack.

Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.

Abstract: A structure and method is disclosed for dissipating electrostatic charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry, and a conductive layer and passivation layers disposed over the underlying dielectric layer wherein the conductive layer diffuses electrostatic charges at the surface of the integrated circuit.

Abstract: Minute surface damage or irregularities on the sensing surface of a capacitive sensor integrated circuit is detected by acquiring a preliminary image of the capacitance readings for the sensor array, coating the sensing surface with an electrolyte solution, then acquiring an additional image while the sensing surface is coated and/or after the electrolyte solution is removed. The electrolyte solution accelerates manifestation of pixel degradation or failure caused by surface damage or irregularities. Defective regions are identified by change of grayscale pixels in the preliminary image while the electrolyte coating is on the sensing surface and then again after the electrolyte coating is removed.

Abstract: An apparatus (and method) is provided that pumps (up or down) the voltage on a memory cell thereby increasing (above the logic one voltage value) or decreasing (below the logic zero voltage value) the voltage stored in the memory cell, and providing an increased differential on the bit lines during a subsequent read operation of the memory cell. When a logic one or zero voltage is coupled to the first plate of the memory cell for storage, the second plate is held at a voltage that is lower or higher, respectively (preferably a voltage that is the complement logic value of the value being stored). After the word line is deactivated (thereby decoupling the memory cell from the bit line and storing a logic one voltage value or logic zero voltage value), the voltage on the second plate is correspondently either raised or lowered. In the present invention, the second plate is raised or lowered to the precharge and equilibrate value (usually Vdd/2).

Abstract: A method is provided for depositing a silicon nitride layer to protect and isolate underlying layers during wet etching. The silicon nitride layer maintains the integrity of interconnect leads, bond pads, and die boundaries by acting as a wet etch stop. The silicon nitride layer stops the chemicals used in a wet etch from reaching underlying layers in the integrated circuit.

Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.