Abstract: A cost-effective anti-howling system and method enables fast detection of the presence of true double talk, and substantially eliminates undesirable howling attributable to sudden changes in the acoustic echo path between a speakerphone microphone and loudspeaker during speakerphone conversations. Speakerphone embodiments include a delay-compensated and normalized cross-product calculation performed by a system processor having at least two memory buffers. One buffer is associated with the loudspeaker signal and the other buffer is associated with the microphone signal. The delay-compensated cross-product of the microphone voice signal input and the loudspeaker voice signal output is determined and normalized by energy estimates of the two signals to reduce the calculation error made by variance in the signal level.

Abstract: A fleet management system for a base station to obtain differential GPS corrections to the location information for the fleet vehicles. A fleet vehicle first sends the information of "position solution" back to the base station with time annotation, where the position solution only needs to specify position, velocity and the satellites observed. The base station, which already has an a priori fixed position vector for its location, generates a potential solution set for all the possibly observable satellites. This allows the base station to vector-process to determine the differential correction for each combinatorial set of satellites observed by the fleet vehicle. This way, equivalent differential GPS accuracy of 10 meters or better can be achieved for the fleet management system without imposing the communications burden to the system.

Abstract: In floating point operations, it is necessary to align the fractions of the floating point operands before addition or subtraction operations can be executed. This fraction alignment is performed by a shifting operation, typically using dedicated apparatus such as a barrel shifter. While the dedicated apparatus provides high performance in the execution of the shifting operation, this performance is accomplished by reserving a portion of the substrate area for apparatus implementation. To avoid the use of dedicated apparatus, the shifting operation is performed in a multiplier unit, according to the present invention, by entering the number to be shifted in the multiplicand register of the multiplier unit while entering appropriate control signals in the multiplier register. In this manner, a shifting operation can be performed without dedicated apparatus and with minor impact on performance.

Abstract: In a multiplier unit implemented with carry/save adder stages and executing a modified Booth algorithm, the signals, required to complete the 2's complement in order to perform a subtraction operation during the multiplication procedure using carry/save adder cells, are entered in the first carry/save stage in the appropriate carry/save cell positions. In this manner, one less signal is processed by the time-critical least significant cell associated with each carry/save adder stage, thereby reducing the overall time delay associated with the multiplier unit and accelerating the multiplication operation.

Abstract: In electronic devices, such as data processing systems that operate at high frequencies, the integrity of the interconnect or coupling apparatus transferring signals between component modules is critical to prevent compromise of information being transferred. However, the interconnect or coupling apparatus is subject to both long term and to short term impedance variations. Apparatus is disclosed for testing both the long term impedance changes and the rapid fluctuations that are not observable by current testing procedures. In addition, apparatus is disclosed for providing controllable rapid impedance changes to verify the operation of test apparatus, disclosed herein, for measuring the rapid impedance changes.

Abstract: The arithmetic operations performed for floating point format numbers involve procedures having a multiplicity of major steps. In the performance of the effective subtraction operation, the determination of absolute value of the difference between the operand exponent arguments must be obtained in order to determine the correct procedure. In the present invention, a difference between a subset of the operand exponent arguments is calculated and the result of this calculation is used to anticipate the correct procedure. By careful selection of the anticipated correct procedure, when the selection is erroneous, the correct result is immediately available. The availabilty of the correct result is achieved by selecting the subset of operand exponent arguments so that, in the event that the result is erroneous, the correct difference is such that the associated operand fraction (i.e., to be shifted by the amount of the difference) is shifted completely out of the operand fraction field (stored in a register).

Abstract: The arithmetic operations performed for floating point format numbers involve procedures having a multiplicity of major steps. The effective subtraction operation can be accelerated by using two methods of execution depending on whether the absolute value of the difference between the arguments of the exponents, ABS{DELTA(E)} is .ltoreq.1 or >1. The procedure for ABS{DELTA(E)}.ltoreq.1 requires more major process steps than the situation where ABS{DELTA(E)}.ltoreq.1. To accelerate only the procedure having more major process steps, the two least significant bits of both exponent arguments are examined and based on the examination, the lengthier procedure can be initiated in parallel with the process step determining the value of ABS{DELTA(E)}. When the lengthier procedure is determined to be inappropriate based on the determined value, the results of the lengthier process can be discarded. Otherwise, the lengthier process, already in progress, is continued.

Abstract: In a floating point arithmetic execution unit, an additional adder unit and a selection network are added to the apparatus typically performing the arithmetic floating point function. The additional apparatus permits certain processes forming part of arithmetic operations to be executed in parallel. For selected arithmetic operations, the final result can be one of two values typically related by an intermediate shifting operation. By performing the processes in parallel and selecting the appropriate result, the execution time can be reduced when compared to the execution of the process in a serial implementation. The fundamental arithmetic operations of addition, subtraction, multiplication and division can each have the execution time decreased using the disclosed additional apparatus.

Abstract: Apparatus and method for expediting the alignment of the fraction portion of operands in floating point operations. The alignment is performed in the arthmetic logic unit where the argument of the operand A exponent is subtracted from the argument of the operand B exponent. Because the result B-A can be a negative quantity, the result A-B can also be required. The arthmetic logic unit of the present invention provides additional apparatus for simultaneously determining B-A and A-B. The additional apparatus includes components in the propagate bit and generate bit cell for determining an auxiliary generate bit; an additional carry-chain array for combining the carry-in signal, the propagate bit and the auxiliary generate bit; and selection circuits for selecting the appropriate result.

Abstract: Apparatus and method are disclosed for identifying and measuring random contact interruption events in a circuit interconnection device. A comparator circuit, adapted to be operated at high frequencies, identifies when an interrupt event has occurred. The comparator circuit, as a result of the interruption event, causes a high frequency counter circuit to count clock pulses. The count in the counter circuit is continuously applied to an RAM memory circuit, write-enabled at an addressed memory location. After the interruption event is terminated, the RAM memory circuit is no longer write enabled at the addressed location and the addressed location is changed (incremented) in preparation for the next event. The counter circuit is also reset to zero in preparation for the next interruption event. The number of counts from a clock unit having a known frequency provides the duration of the interruption event. With the use of a clock unit operated at 100 MHz, interrupt events from 10 nanoseconds to 9.

Abstract: A circuit implemented in CMOS technology that controls the rise and fall times of signals applied to conducting paths of a printed circuit board. The circuit consists of an input inverter circuit stage that controls the slope of an output signal from the inverter stage produced in response to an input signal. A second stage is implemented as a source follower and, in response to the inverter stage output signal, provides the output signal applied to the conducting paths of the printed circuit board. A final stage of the circuit compensates for the inability of the source follower stage to utilize, because of the characteristics of the CMOS field effect transistors, the range of voltages provided by the power supplies. The circuit, by controlling the rise and fall time of signal applied to the printed circuit board, reduces the ringing (i.e. the signal undershoot or overshoot) that can accompany application of pulsed signals to the printed circuit board.

Abstract: In an electronic package in which a fluid is encased to provide efficient thermal transfer between electronic components and cooling plate, the thermal expansion of the cooling fluid is compensated for by tubing in the enclosure. The tubing is vented to the atmosphere and as the cooling fluid expands, the tubing is compressed. The tubing is generally coiled within the chamber and can have a kink in the center region, dividing the tubing into two portions. Both portions of the tubing are vented to the external environment. In the preferred embodiment, surgical tubing is employed to compensate for the thermally induced changes in volume.