Abstract: An subsystem processor for converting an input audio signal to complex audio samples for QADM processing by a modem for communication with a remote modem is disclosed. The audio process comprises a decorrelator for processing the input audio to generate a residual signal, an adaptive scaler for adaptively scaling the residual signal to generate a scaled residual signal, a randomizer for phase-randomizing the scaled residual signal to generate a complex signal with randomized phases, and a limiter for limiting the complex signal with randomized phases, such that the complex signal is transmitted by the modem to a remote modem.

Abstract: A low voltage driver tolerant of high voltage and suitable for driving a processor and a memory device. A first protection NFET is coupled to the drains of a series-coupled PFET and NFET forming the basic driver components. Another protection NFET is connected in series to the first NFET. This second protection NFET requires approximately 1 volt for turn on, such that a resultant 3 volts appear at the output of the complete driver assembly. When the output driver is not enabled and 5 volt inputs are being applied from the memory circuit, the two NFET protection transistors block the 5 volts from reaching the processor output driver.

Abstract: A system and method for providing sound in a computer are disclosed. An audio module for controlling digitized sound I/O is included in a media stream controller. The media stream controller may also coordinate graphics and video which allows multiple media subsystems to be supported from a single bus device. A software application may initiate sound data transfer by sending a conventional DMA mode command to the media stream controller. The media stream controller activates an audio interrupt service routine which processes the request without using a conventional DMA controller. Digital sound data is transferred across a local bus using high speed burst mode block transfer commands and is buffered by the media stream controller in a display memory. Concurrently, the media stream controller may output sound data from the display memory to a sound output device using a double buffering method.

Abstract: An apparatus and a method are provided to obtain oscillations from a crystal at a particular frequency by introducing real and imaginary components of voltage to the crystal. The imaginary component of voltage is different from the real component of voltage by a particular phase angle such as 90.degree.. The voltage introduced to the crystal is processed to produce a first current having characteristics corresponding to such voltage and to produce a second current having characteristics related to the imaginary component of such voltage. The first and second currents are combined to produce a first current corresponding to the real component of the voltage introduced to the crystal. This current is shifted through a phase angle of 90.degree. to produce a second current corresponding to the imaginary component of the voltage introduced to the crystal. The first current is converted to a first voltage which is regulated to provide a particular gain.

Abstract: A frequency error calibration, estimation and compensation device and method for direct sequence spread spectrum systems, such as digital cordless telephones having a handset and a base station. Initial frequency calibration occurs when the handset is physically coupled to the base station. The allowable frequency error range is divided into a plurality of frequency bins. Both the handset and base station transmit and receive messages using a predetermined frequency offset bin as an estimate of the frequency error. A signal quality value is determined and then a next bin is selected and a next signal quality value is determined. Once a signal quality value has been determined for each frequency bin, a communications link is established between the handset and the base station to allow automatic frequency control tracking to fine tune the frequency offset value. If the signal quality is not above a threshold value, the procedure is repeated.

Abstract: An adaptive frequency correction burst detector for GSM handset systems in a wireless communication system is disclosed. The detector uses a bandpass filter to filter the complex received samples to generate a first filtered output r(n). The first filtered output is then applied to a notch filter for the notch filter to adaptively generate a second filtered output y(n). An error calculation unit is used for calculating an error signal based on the difference between the second filtered output y(n) and a desired signal d(n), which is zero in the case of a notch filter. A notch filter coefficient updating unit is used for adaptively updating the notch filter using a least-mean-square algorithm. Then an error power is estimated based on the second filtered output y(n), while the signal power is estimated based on the first filtered output r(n).

Abstract: A system for processing a stream of data and automatically selecting a portion or all of the data stream for block writing to a memory. The memory is capable of storing data in response to a block write command and a normal write command. The system contains a first data register and a second data register having the same data width. The first data register accepts data from the data stream in accordance with the its data width. Data stored in the first data register is transferred to the second data register. The first data register is then loaded with a portion of the data stream which is contiguous to the data stored in the first data register prior to the transferring. The data in the first and the second data registers is then compared. If the data in the first and the second registers is the same, then the content of a data counter is increased by one. When the content of the data counter exceeds a predetermined value, the system executes a block write command.

Abstract: A CPU introduces software commands to a first limited capacity memory (e.g. FIFO), on an integrated circuit chip. Data (e.g. graphics) from a first portion of a second memory (off chip) is processed in accordance with such commands. A second portion (e.g. FIFO) of the second memory may also store commands normally passing from the CPU through the first memory. When the first memory becomes full, the commands may pass from the CPU through the second portion of the second memory (which may have a storage capacity considerably greater than that of the first memory) and then through the first memory. The commands may continue to flow in this auxiliary path until the second portion of the second memory becomes empty. A third memory of a limited capacity on the chip may pass the commands from the CPU to the first memory in the normal operation or to the second portion of the second memory when the first memory becomes full. The CPU may also pass commands to other peripheral equipment while a ready line is high.

Abstract: An improved frame structure for use in mobile communications systems utilizing slotted protocols is provided. According to the present invention, consecutive slots in a frame are assigned to each mobile unit so that the mobile unit transmits to a base station during the first slot and receives a transmission from the base station during the second slot. This frame structure, permits the mobile unit to monitor various frequencies for a longer and more continuous period of time. It is important for the mobile unit to have enough time to monitor frequencies while it is not transmitting or receiving so that base station handoff and interference avoidance handoff techniques can be performed by the mobile communications system. Furthermore, according to the frame structure provided by the present invention, the mobile units can be designed with a standard frequency synthesizer.

Abstract: A resolution conversion system for real-time expansion and reduction of a first plurality of input pixels into a second plurality of output pixels. The resolution conversion system comprises a base-n counter for counting input pixels as each pixel is captured. The base-n counter has a plurality of carry out signals. Also, there is a control register for selectively enabling the carry out signals of the base-n counter based on a predetermined resolution ratio between the first plurality of input pixels and the second plurality of output pixels. The control register uses a mode bit to select either one of inserting and removing operations. An inserting logic unit is used for inserting, as indicated by the mode bit, a pixel into the plurality of input pixels upon a transition of one of the carry out signals if the carry out signals have been enabled by the control register.

Abstract: Multiple speech bit-stream frame buffers are used between the controller and the speech decoder. Whenever excessive or missing speech packages are detected, the speech decoder switches to a special corrective mode. If there is too much, the buffered frames are played out fast; if there is too little the buffered frames are played out slowly. For the fast play, some speech information has to be discarded, while for the slow play some speech-like information has to be synthesized. The speech may be handled in sub-frame units, which may be 52 samples at a time. Low energy, silent or unvoiced sub-frames, which also indicate non-periodicity, are detected and manipulated. Moreover, the decoded signal is manipulated at the excitation phase, before the final LPC synthesis filter, resulting in a transparent perceptual effect on the manipulated speech quality. Additionally, the buffers are enlarged such that the problem caused by controller asynchronicity is eliminated.

Abstract: The present invention provides methods for combining antenna diversity and gain control in a communications system using a single chain of receiver electronics. A number of input parameters related to various characteristics of a received signal are used to determine the quality of the received signal. The antenna diversity and gain control procedures are enabled or disabled based on the signal quality. The antenna diversity procedure estimates the signal level of the non-operational antenna using an infinite impulse response digital filter. The gain control procedure selects one of three gain paths based on the received signal strength.

Abstract: A variable speed playback system exploits multiple-period similarities within a residual signal, and includes multiple-period template matching which may be applied to alter the excitation periodical structure, and thereby increase or decrease the rate of speech playback. Embodiments of the present invention enable accurate fast or slow speech playback for store and forward applications without changing the pitch period of the speech. A correlated multiple-period similarity measure is determined for an excitation signal within a compressor/expander. The multiple-period similarity enables overlap-and-add expansion or compression by a rational ratio. Energy variations at the onset and offset portions of the speech may be weighted by energy-based adaptive weight windows.

Abstract: A method for efficient coding of non-active voice periods is disclosed for a speech communication system with (a) a speech encoder, (b) a communication channel and (c) a speech decoder. The method intermittently sends some information about the background noise when necessary in order to give a better quality of overall speech when non-active voice frames are detected. The coding efficiency of the non-active voice frames can achieved by coding the energy of the frame and its spectrum with as few as 15 bits. These bits are not automatically transmitted whenever there is a non-active voice detection. Rather, the bits are transmitted only when an appreciable change has been detected with respect to the last time a non-active voice frame was sent. To appreciate the benefits of the present invention, a good overall quality can be achieved at rate as low as 4 kb/s on the average during normal speech conversation.

Abstract: A circuit for resetting an electronic system based on voltage fluctuations in the power supply is disclosed. The circuit comprises a diode means for generating a first voltage being offset from the supply voltage, a first inverter having its input connected to the diode and powered by a reference voltage source, a second inverter having its input connected to the same reference voltage source and powered by the power supply; and an OR- or NOR- gate having its inputs from the outputs of the first and second inverters, such that its output, when asserted, resets the electronic system.

Abstract: A conventional CELP speech codec synthesizes a pitch interval in a sound by synthesizing a scaled innovation signal--typically, a random signal--and adding it to a scaled pitch signal derived from the synthesized speech of the previous pitch interval. This invention continues this practice when it is advantageous, but, at the onset of the sound or whenever else needed, replaces the scaled innovation signal with a scaled spike signal. This is done since a spike is sometimes more useful than an innovation signal is, innovation signals being by definition crafted to instead represent differences between adjacent pitch intervals within a sound rather than at the onset of a sound.

Abstract: The present invention provides methods for combining antenna diversity and gain control in a communications system using a single chain of receiver electronics. A number of input parameters related to various characteristics of a received signal are used to determine the quality of the received signal. The antenna diversity and gain control procedures are enabled or disabled based on the signal quality. The antenna diversity procedure estimates the signal level of the non-operational antenna using an infinite impulse response digital filter. The gain control procedure selects one of three gain paths based on the received signal strength.

Abstract: A register file connected to a data memory and an arithmetic logic unit for temporary storage of operands, and a method of managing such register file permits the register file to be used to maximum efficiency, and permits rapid task and context switching. Each register of the register file has an absolute address. A relative register address is read from the address field of the instruction being executed by the ALU, and an arithmetic calculation is performed on that relative register address and a register base address to obtain an absolute register address of the register to be accessed. Different sets of registers may be designated for different tasks or contexts. Each set of registers has its own base address. Once the task or context to which the instruction applies is determined, a calculation using the relative address from the instruction address field, and the corresponding register set base address may be performed to obtain the absolute address of the register to be accessed.

Abstract: A single clamp circuit for integrated circuits with multiple V.sub.dd power pins by coupling the various V.sub.dd busses to an ESD clamped V.sub.dd bus or pseudo- V.sub.dd bus via diodes. The diodes will provide coupling from any V.sub.dd bus to the clamp circuit during a positive ESD transient. A diode for each V.sub.dd bus and a single clamp circuit can be much more area efficient than a single clamp circuit for each V.sub.dd bus. During normal operation, the diodes will become weakly forward biased due to the leakage current of the clamp circuit. Small signal noise will tend not to be coupled from one bus to the other because of the high impedance of the diodes. For a large positive noise transient on one bus, the other bus diode will reverse bias, thus decoupling the signal from the other busses. A large negative noise transient on one bus will cause its diode to reverse bias thus decoupling it from the other busses.

Abstract: The present invention provides methods for combining antenna diversity and gain control in a communications system using a single chain of receiver electronics. A number of input parameters related to various characteristics of a received signal are used to determine the quality of the received signal. The antenna diversity and gain control procedures are enabled or disabled based on the signal quality. The antenna diversity procedure estimates the signal level of the non-operational antenna using an infinite impulse response digital filter. The gain control procedure selects one of three gain paths based on the received signal strength.