Abstract: A fault isolation system for use in an integrated circuit. The fault isolation system includes multiple input shift registers which are connected end-to-end, serial output to serial input, for convenient interface with a test data input and test data output that are controlled by the test access port controller (tap controller) of conventional JTAG circuitry that is frequently provided in such integrated circuits. The multiple input shift registers include parallel inputs which receive test data from test nodes within functional blocks such as general circuit blocks and linear bus alleys. The multiple input shift registers are efficiently controlled by a global controller which talks to many local controllers. The global controller distributes control signals that are received by the local controllers.

Abstract: A pitch estimation device and method utilizing a multi-resolution approach to estimate a pitch lag value of input speech. The system includes determining the LPC residual of the speech and sampling the LPC residual. A discrete Fourier transform is applied and the result is squared. A lowpass filtering step is carried out and a DFT on the squared amplitude is then performed to transform the LPC residual samples into another domain. An initial pitch lag can then be found with lower resolution. After getting the low-resolution pitch lag estimate, a refinement algorithm is applied to get a higher-resolution pitch lag. The refinement algorithm is based on minimizing the prediction error in the time domain. The refined pitch lag then can be used directly in the speech coding.

Abstract: A method and system for encoding an input signal for storage or transmission over a communications channel by transforming successive vectors of parameters of the input signal into a corresponding succession of index signals, each index signal being associated with a quantized vector that corresponds to an ordered set of values of the input signal parameters.

Abstract: The magnitudes of an input voltage and individual ones of progressive fractions of a reference voltage are compared to produce first and second output voltages. Each of the elements in a first logical network receives the first output voltage from an individual one of the comparators and the second output voltage from a comparator non-consecutive with (preferably 2 comparators removed from) such individual comparator. Signals from these elements pass to latches. The latches have assertion and negation outputs which pass to elements in a second logical network. When an individual one of the elements in the second logical network provides a particular output, it prevents the elements receiving outputs from comparators responsive to lower reference voltage fractions from providing the particular output.

Abstract: A direct sequence spread spectrum communication system in a digital cordless telephone having a basestation and a handset that each implement an extended .linevert split.EE.linevert split.+.linevert split.E.linevert split.-.linevert split.L.linevert split.-.linevert split.LL.linevert split. time tracking system and peak matched filter demodulation within a related window to permit one sample per chip analog-to-digital conversion and demodulation for longer code sequences (providing savings in hardware and complexity) and to permit enhanced two sample per chip analog-to-digital conversion and demodulation for shorter code sequences (providing more robust fading immunity).

Abstract: A system and method for generating composite video signals in a computer. Digital pixel data may be processed by software to form component video pixel data, which may include luminance and chrominance components. A chrominance look-up table is provided in a display memory and is used for modulation of the chrominance components. The modulated components are then combined to form digital composite video pixel data which may be stored in a frame buffer in the display memory. Video control information is precalculated and stored in the display memory in advance. The digital composite video pixel data and video control information are then recovered from the display memory to produce a formatted stream of video data. The architecture of this system greatly reduces hardware complexity and bandwidth requirements. In addition, the process may be controlled by a media stream controller which is also adapted for audio and graphics processing.

Abstract: A space vector data path for integrating SIMD scheme into a general-purpose programmable processor. The programmable processor uses a mode field in each instruction to specify, for each instruction, whether an operand is processed in either one of vector or scalar modes. The programmable processor also has a plurality of sub-processing units for receiving the operand and, responsive to an instruction as specified by the mode field in each instruction, for processing the operand in either one of the vector or scalar modes, wherein the vector mode indicates to the plurality of sub-processing units that there are a plurality of elements within the operand and the scalar mode indicates to the plurality of sub-processing units that there is but one element within the operand. For the vector mode, each element is processed by one of the sub-processing units concurrently to generate a vector result.

Abstract: A multi-purpose current source which provides both a PTAT and a constant current source and which requires only one precision external or laser trimmed resistance. The PTAT constant current circuit includes a differential amplifier having one input coupled to a V.sub.PTAT reference voltage and the other input coupled to a V.sub.bg scaling circuit. The tail current for the differential amplifier is held constant at the current level of an associated constant current source based upon V.sub.bg. Therefore, the amount of current output from the PTAT current source will be dependent upon the current of the constant current source, rather than upon a resistance value. By setting the scaling circuit appropriately, the current that flows through the output leg of the differential amplifier in the PTAT current source when the ambient temperature is equal to 25.degree. C. will be equal to one half the tail current through the differential amplifier, and thus one half the current output from the constant current source.

Abstract: An apparatus and method of quantizing a sequence of input data vectors using delayed decision switched prediction and vector quantization. The method has the following steps of operation: (a) predicting a next vector element from said sequence of input data vectors to generate a set of prediction vectors; (b) subtracting the set of prediction vectors from the next vector element to generate a set of prediction error vectors; (c) multi-stage vector quantizing the set of prediction error vectors to generate a set of quantized prediction error vectors with each of the stages having at least one of the tables and local decision means to generate a final quantization error vector according to a predetermined distance measure; (d) selecting one predictor out of the set of predictors from the switched prediction step and selecting, for each of the stages, at least one entry from the set of tables of the vector quantization step according to the predetermined distance measure, generating a quantized data vector.

Abstract: A method is disclosed for generating frame voicing decisions for an incoming speech signal having periods of active voice and non-active voice for a speech encoder in a speech communication system. The method first extracts a predetermined set of parameters from the incoming speech signal for each frame and then makes a frame voicing decision of the incoming speech signal for each frame according to a set of difference measures extracted from the predetermined set of parameters. The predetermined set of extracted parameters comprises a description of the spectrum of the incoming speech signal based on line spectral frequencies ("LSF"). Additional parameters may include full band energy, low band energy and zero crossing rate.

Abstract: A header and a payload in a cell are separated for transfer between a cell interface and a host memory. The header is transferred to a control memory. For transfer to the host memory, the control memory initially provides a host-memory region address and the region length. The payload is recorded in such region. The control memory also provides a second host-memory region address, and length, when the payload length exceeds the payload length in the first address region. For transfer from the host memory to the cell interface, the control memory provides a host memory region address and the header combines the header and the payload and passes the combination to the cell interface. Cells from different sources (i.e. terminals) are scheduled at table positions dependent upon their individual transfer rates. The cells at the scheduled positions are normally transferred in time slots corresponding to such positions.

Abstract: A method of digital data transmission between a first transceiver and a second transceiver is disclosed. The first transceiver has a first transmitter and a first receiver and the second transceiver has a second transmitter and a second receiver. The first transmitter also contains a programmable encoder for encoding its transmission, while the second receiver uses at least one of a plurality of error correcting codes (ECC's) for decoding its reception. Each ECC can be specified by a predetermined set of parameters.

Abstract: A cordless telephone system connectable to the public switched telephone network having a base station and one or more handsets communicating with the base station by an RF link utility time division duplex direct sequence spread spectrum modulation technique, having a digital variable rate automatic gain control loop. The gain is varied by changing the scale factor for the discriminator output. A high gain scale factor is used during signal acquisition. When the signal has been acquired, a low scale factor is utilized during signal tracking. The controller in the base station and in the handset causes gain use of the different scale factor at the appropriate time.

Abstract: The noise from the effects of currents through distributed capacitances between electrical circuitry on an integrated circuit chip and the chip substrate is minimized, especially for analog circuitry mixed on the chip with digital circuitry. The invention separates a plurality of bits in each digital word into a plurality (e.g. 2) of segments. A first register off the chip latches the first bits in each word with a first clock signal. A second register off the chip latches the second bits in each word with a second clock signal delayed from the first clock signal. The first register bits are latched on the chip with the first clock signal by a third register. The delayed second register bits are latched on the chip by a fourth register with the second clock signal or with a delayed first clock signal having the same delay as the second clock signal. Substrate ties for the third and fourth registers may be connected to at least one, preferably a plurality, of bonding pads on the chip.

Abstract: A testing and evaluation system for efficiently qualifying individual components of a modem. A modem data pump acts as a dBm meter by measuring distortion, noise floor, and echo. The modem is coupled to a computer and a remote modem. After calibration, the remote modem may be disconnected. A resistor having a preselected resistance is coupled to the modem to allow the computer to measure the modem noise floor and distortion independent of particular telephone connections. An echo canceler coupled to the receive line allows the sum distortion and noise to be measured.

Abstract: A multiplexer, preferably on an integrated circuit chip, receives a plurality of buses each having a plurality of lines responsive to binary indications and passes the binary indications in the lines of a particular one of the buses. The multiplexer includes a plurality of circuit blocks each responsive to the binary indications in the lines of an individual one of the buses. Each block has a plurality of recursive circuits each having first and second stages. The second stages of the recursive circuits in an individual one of the circuit blocks receive an individual one of a plurality of control indications at a first side of the block to activate the first stages in such recursive circuits. The first stage in each recursive circuit in each individual circuit block receives at a second side of the block the binary indications in an individual line in an individual one of the buses to obtain a signal from such first stage in accordance with such binary indication upon the activation of such first stage.

Abstract: A method and apparatus for iterative carrier frequency estimation of a base station by a mobile station in a wireless communication system is disclosed. Upon detecting a frequency correction burst ("FCB") signal from the wireless transmission of the base station, the mobile station first buffers the FCB signal and then filters the buffered signal with a bandpass filter to generate a first set of filtered data. After filtering, the first filtered data is again filtered with an auto-regressive filter to generate a corresponding set of second filtered data. With the second filtered data, iterative pole estimation of the AR filter and filtering by the AR filter is made for a predetermined set of iterations to generate a converged pole estimate, which can then be used to derive the carrier frequency of the base station.

Abstract: A method for testing a communication link between first and second components of a system, which components communicate via a selected one of a plurality of broadcast channels, the second component being powered by a self-contained power source, the method comprising: causing the first component to scan a plurality of the broadcast channels in sequence in a receiving mode during a scanning period and to broadcast a test signal over the selected channel during the scan; and maintaining the second component in an inactive state in which energy consumption is minimized and in which the second component is unresponsive to broadcast signals during a major part of the scanning period, placing the second component in an active state in which the second component can detect the test signal during a time when the test signal is being broadcast, and causing the second component to broadcast a response signal upon detection of the test signal.

Abstract: The present invention relates to circuitry for a receiver having a low cost filter using automatic alignment of the center frequency of signals input to the filter to suppress noise and out-of-band signals from the filter output over a narrow bandwidth. An RF input signal to the receiver is downconverted to an IF frequency using a VCO, and the IF signal is provided to the low cost filter. The output of the filter is input to a frequency correction circuit and a distortion detection circuit. The distortion detection circuit provides an error signal including positive frequency shift errors determined from digital ones identified from the filter output signal, and negative frequency shift error signals determined from digital zeros in the filter output signal.

Abstract: A circuit for reducing switching noise caused by harmonics of an output coupled to a band of interest in a mixed signal communication device, with the mixed signal communication device having a predetermined sampling clock.