Abstract: A system that increases device yield by correcting improper operation of the device's memory cells due to process variations is disclosed. The device includes an array of memory cells and an adjustable bias voltage circuit, and is coupled to a test circuit that generates a feedback signal indicating whether one or more of the memory cells fail to operate properly. The adjustable bias voltage circuit selectively adjusts a bias voltage tied to the substrate provided to the memory cells in response to the feedback signal to alter the operating characteristics of the memory cells so that all of the memory cells will operate properly. For some embodiments, a plurality of fuses are provided for storing control signals that control the bias voltage provided to the memory cells.

Abstract: An FPGA includes a plurality of configurable logic elements, a configuration circuit, a decryption circuit, and a fingerprint element. The fingerprint element generates a fingerprint that is indicative of inherent manufacturing process variations unique to the FPGA. The fingerprint is used as a key for an encryption system that protects against illegal use and/or copying of configuration data. In some embodiments, the propagation delay of various circuit elements formed on the FPGA are used to generate the fingerprint. In one embodiment, the specific frequency of an oscillator is used to generate the fingerprint. In some embodiments, a ratio of measurable values may be used to generate the fingerprint. In other embodiments, differences in transistor threshold voltages are used to generate the fingerprint. In still other embodiments, variations in line widths are used to generate the fingerprint.

Abstract: A system measures propagation delays in any number of test circuits, each having two asynchronous inputs and an output, without using their clock inputs to re-initialize the test circuits during measurement operations. The delay between one of the test circuit's asynchronous inputs and its output is measured by propagating a test signal from the one asynchronous input to the output, and the test circuit is re-initialized using the test circuit's other asynchronous input.

Abstract: The present invention incorporates level-shifting functions within a multiplexer circuit that may be implemented in IC devices having low and high voltage domains. The multiplexer circuit utilizes pseudo-differential multiplexing architectures and employs level-shifting techniques to convert low-voltage signals received from the low-voltage domain into high-voltage signals more suitable for controlling the propagation of a selected input signal through the pass gates of the multiplexer circuit. For some embodiments, some of the select signals may be decoded to generate a number of decoded select signals that can be used to control the selective routing of signals through the multiplexer.

Abstract: A traffic management processor for processing different types of traffic flows includes a departure time calculator (DTC) circuit for calculating a departure time for each packet received, a content addressable memory (CAM) device coupled to the DTC circuit and having a plurality of rows, each row including a first portion for storing the departure time for a corresponding packet and including a second portion for storing a bit indicating a traffic type for the packet, and compare logic coupled to the CAM device and configured to determine which of the departure times stored in the CAM device is the earliest.

Abstract: A traffic management processor that selectively throttles individual traffic flows or particular traffic types specified in a throttle control instruction, which may also cause the traffic management processor to throttle all network traffic.

Abstract: A traffic management processor for managing a number of traffic flows each including one or more packets includes a content address memory (CAM) device having a plurality of rows, each row storing a flow identification (ID) for a corresponding packet, the flow ID indicating to which traffic flow the packet belongs, a departure time table for storing departure times for the packets, and compare logic for comparing the departure times with each other to determine which departure time is the earliest.

Abstract: A CAM device having a plurality of CAM blocks includes circuitry to disable one or more defective CAM blocks, and to selectively translate address space in the disabled CAM blocks to the remaining enabled CAM blocks. In one embodiment, each CAM block is coupled to a corresponding block select circuit and to an address translation circuit. Each block select circuit provides a select signal to a corresponding CAM block to selectively enable or disable the CAM block. The address translation circuit includes logic that translates address space from disabled (e.g., defective) CAM blocks to enabled (e.g., non-defective) CAM blocks. During read and write operations, an address to access a row in a first of the CAM blocks is received into the address translation logic. If the first CAM block is disabled, the address translation logic translates the address to access a row in a second of the CAM blocks.

Abstract: A bandgap reference voltage circuit includes a bandgap circuit, a start-up circuit, and a recovery circuit. Upon device power-on, the start-up circuit provides a start-up current to initialize the bandgap circuit to a valid state, during which the bandgap circuit generates a substantially constant bandgap reference voltage. Once the bandgap circuit is in the valid state, the start-up circuit turns itself off. If the bandgap reference voltage falls to a level that causes the bandgap circuit to enter an invalid state, the recovery circuit turns on and provides a recovery current to the bandgap circuit that returns the bandgap circuit to the valid state, after which the recovery circuit turns itself off.

Abstract: An integrated circuit such as an FPGA containing an embedded processor having test circuitry capable of controlling the processor's resources using JTAG commands includes a formatting circuit that formats soft data received from an external storage device into a JTAG-compatible bitstream that can be used by the processor's test circuitry to access and/or control the processor's resources at any time, thereby allowing the embedded processor's resources to be accessed and controlled during FPGA configuration operations before the processor has been initialized to an operational state without using an external configuration tool. For some embodiments, the formatting circuit is a state machine that formats soft data such as firmware code, software programs, processor commands, and the like received from the external storage device into a JTAG-compatible bitstream that can be loaded into and/or used to access the resources of the embedded processor via the processors' test circuitry.

Abstract: A voltage supply circuit for generating a composite bandgap reference voltage includes a single bandgap reference voltage circuit and a select circuit. The bandgap reference circuit has a first output to generate a first bandgap voltage having a first temperature coefficient and has a second output to generate a second bandgap voltage having a second temperature coefficient that is different from the first temperature coefficient. The select circuit has a first input to receive the first bandgap voltage, a second input to receive the second bandgap voltage, and an output to selectively provide either the first bandgap voltage or the second bandgap voltage as the composite bandgap reference voltage.

Abstract: A control circuit generates a temperature-dependent gate voltage for turning on a transistor. For NMOS transistors, the gate voltage is increased in response to decreases in temperature to compensate for corresponding increases in the transistor's threshold voltage, and is decreased in response to increases in temperature to compensate for corresponding increases in the transistor's gate oxide's susceptibility to breakdown. For PMOS transistors, the gate voltage is decreased in response to decreases in temperature, and is increased in response to increases in temperature. For some embodiments, the gate voltage is adjusted according to a predetermined relationship between gate voltage and temperature.

Abstract: A traffic management processor configured to selectively terminate individual traffic flows includes an instruction decoder to receive a termination instruction specifying which traffic flows are to be deleted, and a content addressable memory device having a plurality of rows, each including a flow ID and termination bit for a corresponding packet.

Abstract: A standardized test head assembly for testing a plurality of integrated circuit dice each having a different bonding pad footprint, the test head assembly including an arrangement of probe holes defined by a predetermined configuration of contact positions, wherein the predetermined configuration defines each of the different bonding pad footprints so that during testing the probe holes align with a subset of the bonding pads for each of the different bonding pad footprints.

Abstract: A memory includes a plurality of row segments, with each row segment having a number of memory cells coupled to a corresponding dataline segment pair. Dataline driver circuits are provided between row segments to buffer signals on adjacent dataline segments. A control circuit is coupled to at least one row segment, and provides control signals to the at least one row segment and to the dataline driver circuits.

Abstract: A content addressable memory (CAM) device. For one embodiment, the CAM device includes a CAM array having a plurality of columns of CAM cells, a plurality of storage elements, each for storing a column pass/fail signal indicating whether a corresponding column of CAM cells is designated as good or as bad, and a test circuit having an output coupled to the storage elements, and configured to generate the column pass/fail signals during a column test sequence.

Abstract: An integrated circuit (IC) device includes a first voltage supply for powering first circuitry within the device, a second voltage supply for powering second circuitry within the device, a suspend circuit having an output to generate a power-down signal, and a voltage regulator circuit coupled to a power node. The voltage regulator circuit includes a first transistor coupled between the first voltage supply and the power node and having a gate responsive to a regulation signal, a second transistor coupled between the second voltage supply and the power node and having a gate responsive to the power-down signal, and a well bias circuit having an input coupled to receive the power-down signal, a first output coupled to a well region of the first transistor, and a second output coupled to a well region of the second transistor.

Abstract: A traffic management processor includes a departure time calculator for generating a departure time for each packet, a departure time table having a plurality of rows, each having a first portion for storing the departure time for a corresponding packet and having a second portion for storing a rollover bit, and a reset circuit configured to reset the rollover bits in a predetermined time.

Abstract: A content addressable memory includes a plurality of CAM blocks, each including an array of CAM cells to store a predetermined range of data values, a parsing circuit having an input to receive the search key and having an output to provide a selected portion of the search key in response to a select signal, and a plurality of block select circuits, each configured to enable a corresponding CAM block if the selected portion of the search key falls within the predetermined range of data values for the corresponding CAM block.

Abstract: A CAM includes a plurality of CAM blocks, each including an array of CAM cells divided into a plurality of segments, each array segment for storing a number of data values that are assigned the same priority, a plurality of block priority circuits, each having inputs to receive match signals from a corresponding CAM block and having outputs to generate a block index and priority of a matching data value in the corresponding CAM block assigned the highest priority, and a global priority and index circuit having inputs to receive the block indexes and associated priorities from the block priority circuits, and having an output to generate a device index and associated priority of the highest priority matching value.