Abstract: A bit line control circuit is coupled between a bit line of an associated Content Addressable Memory (CAM). Array and a supply voltage. The bit line control circuit adjusts the charge current for the bit line in response to a bit line control signal. For some embodiments, the bit line control circuit includes a dynamic component and a static component to control the bit line.

Abstract: A bicycle seat assembly includes a tubular seat post having an upper serrated surface, a threaded aperture formed in the upper serrated surface and aligned with a longitudinal axis of the tubular seat post, a saddle support structure having a lower serrated surface adapted to mate with the upper serrated portion of the tubular seat post, the lower serrated portion including a slot through which a bolt can extend and mate with the threaded aperture, and a saddle adapted to mate with an upper surface of the saddle support, the saddle having a opening formed therein that allows access to the bolt through a top surface of the saddle.

Abstract: A programmable logic device (PLD) includes columns of block memory interposed between columns of configurable logic blocks (CLBs). Each column of block memory includes a plurality of random access memories (RAMs) that share common configuration address lines that do not allow the RAMs in block memory column to be individually addressed. For some embodiments, each RAM in the column includes interface logic that selectively enables the RAM during configuration operations in response to a configuration enable bit, which may be provided to the PLD in a configuration bitstream and stored in a shadow register associated with the RAM.

Abstract: An interface structure includes first and second portions. The first portion has physical dimensions that are compatible with the docking area of an associated device tester, and includes a first socket configured to receive a first BGA package. The second portion, which is adjacent to and contiguous with the first portion, extends laterally beyond the docking area of the device tester to provide additional testing area that may include one or more additional sockets. In one embodiment, the second portion includes a second socket configured to receive a second BGA package, wherein the second size and configuration of second BGA package are different from the size and configuration of the first BGA package.

Abstract: A technique for digital video processing in a predictive manner is provided. In one embodiment, a method for processing digital video signals for live video applications comprises providing video data that comprise a plurality of frames, identifying a first frame and a second frame in the frame sequences, and processing the information of the first frame and the information of the second frame to determine a quantization step for the second frame. The step of processing the information of the first frame and the information of the second frame further comprises calculating a sigmaSAD value for the second frame, calculating a divisor value for the second frame, and calculating the quantization step for the second frame. In another embodiment, a system for processing digital video signals for live video applications comprises a memory unit within which a computer program is stored. The computer program instructs the system to process digital video in a predicative manner.

Abstract: A content addressable memory (CAM) cell including a memory cell coupled to a word line, a compare circuit coupled to the memory cell and to a match line, and a driver circuit having an input coupled to the match line and an output coupled to the word line.

Abstract: A monolithic Multi-chip Module (MCM) package includes two or more individual CAM dice mounted on a substrate formed as, for example, a plastic ball grid array (PBGA) package. The substrate includes an interconnect structure to route signals between corresponding pads of the CAM dice and balls of the MCM package. In some embodiments, the footprint of the MCM ball grid array package is identical to the footprint of a similar PBGA package housing a single CAM die. Each CAM die within the MCM package may be assigned the same device identification number (DID).

Abstract: A content addressable memory (CAM) has a main array including a plurality of rows of CAM cells, one or more spare rows of CAM cells selectable to functionally replace defective rows of CAM cells in the main array, and a control circuit for disabling the defective rows by writing predetermined data to the defective rows of CAM cells.

Abstract: A high-speed I/O driver includes circuitry that is configurable to meet single-ended and differential I/O signal standards. For one embodiment, the driver includes four input circuits that can be configured to implement two CMOS inverters to process single-ended signals or configured to implement a differential circuit to process differential signals.

Abstract: A memory device includes a memory array, a first protocol circuit, a second protocol circuit, an operation interface, and a protocol detection circuit. The first protocol circuit, which implements a first communication protocol, and the second protocol circuit, which implements a second communication protocol, are coupled in parallel between the memory array and the operation interface. The protocol detection circuit, which is coupled to the operation interface and to the first and second protocol circuits, monitors control signals provided to the operation interface by a host controller to determine which communication protocol the host controller employs. In response thereto, the protocol detection circuit selects one of the first and second protocol circuits to handles communication between the host controller and the memory device.

Abstract: A word line driver circuit is coupled to a word line of an associated Content Addressable Memory (CAM) array. The word line driver circuit adjusts the word line read voltage in response to a compare signal indicative of whether the CAM array is performing a concurrent compare operation. For some embodiments, the word line driver circuit selectively provides a relatively high word line read voltage or a relatively low word line read voltage in response to the compare signal.

Abstract: A memory device having single event upset (SEU) resistant circuitry includes a first inverter having an input and an output, a second inverter having an input and an output, a first transistor having a gate coupled to the input of the first inverter and having source and drain regions coupled to the output of the second inverter, and a second transistor having a gate coupled to the input of the second inverter and having source and drain regions coupled to the output of the first inverter.

Abstract: An input buffer circuit includes a first differential circuit, a second differential circuit, a pull-up circuit, and a pull-down circuit. An input voltage and a reference voltage are provided to the first and second differential circuits. The first differential circuit detects rising edges of the input voltage and causes the pull-up circuit to quickly drive an output voltage to logic high. The second differential circuit detects falling edges of the input voltage and causes the pull-down circuit to quickly drive the output voltage to logic low.

Abstract: A termination resistor circuit includes a first and second passive resistive elements coupled in series between a common mode voltage and a signal node, and a plurality of active resistive elements coupled in parallel with the first passive resistive element. The active resistive elements may be selectively enabled by corresponding control signals to provide various numbers of parallel resistances across the first passive resistive element, thereby tuning the termination resistor circuit to a desired resistance value.

Abstract: A content addressable memory (CAM) having a main array including a plurality of columns of CAM cells, a spare column of CAM cells selectable to functionally replace a defective column of CAM cells in the main array, and circuitry to shift data corresponding to the defective column and data corresponding to all subsequent columns to corresponding adjacent non-defective columns.

Abstract: A match line control circuit includes a match line control circuit coupled between a match line of a row of an associated CAM and a supply voltage. The match line control circuit adjusts the charge current for the match line in response to a valid bit and a pre-charge signal. For some embodiments, the match line control circuit includes a dynamic component and a static component to control the match line.

Abstract: A programmable logic device includes a function block to generate a power control signal that is distributed on a rail to selectively power down various components on the device. The rail is coupled to an observation pin to allow for external observation of the power control signal. The power control signal is also provided as a feed forward signal to an input signal blocking circuit, which selectively enables or disables the device input pins in response to the feed forward signal. The feed forward signal is not accessible from the observation pin, and therefore cannot be externally altered from the observation pin.

Abstract: A CAM device having plurality of CAM blocks includes circuitry to disable one or more defective CAM blocks, and to selectively translate address space in the disabled CAM blocks to the remaining enabled CAM blocks. In one embodiment, each CAM block is coupled to a corresponding block select circuit and to an address translation circuit. Each block select circuit provides a select signal to a corresponding CAM block to selectively enable or disable the CAM block. The address translation circuit includes logic that translates address space from disabled (e.g., defective) CAM blocks to enabled (e.g., non-defective) CAM blocks. During read and write operations, an address to access a row in a first of the CAM blocks is received into the address translation logic. If the first CAM block is disabled, the address translation logic translates the address to access a row in a second of the CAM blocks.

Abstract: A small, substantially flat, envelope-shaped scent dispensing packet contains a porous, absorbent scent emitting material which retains a desired scent or fragrance. Compressing the packet forces scent-laden air within the packet through an opening in the packet, thereby delivering the scent to a user.

Abstract: A CAM system includes two or more CAM devices having the same device identification number (DID). One or more priority address bits indicating priority between the CAM devices may be assigned to each CAM device. Each CAM device may receive a mode signal indicating whether the CAM device operates independently or in cooperation with other cascaded CAM devices. During compare operations, each CAM device generates a highest priority match (HPM) index. A selected number of the priority address bits are inserted between the DID and the HPM index to form a device index for the system. During read and write operations, a first portion of an input address is used to select a row of CAM cells in each CAM device. A second portion of the input address is compared to a selected number of the priority address bits to enable an array in one of the CAM devices.