Abstract: A sense amplifier includes cross-coupled latch has a PMOS bias transistor for selectively connecting the cross-coupled latch to a supply voltage and has an NMOS bias transistor for selectively connecting the cross-coupled latch to ground potential. The conductivity of the PMOS bias transistor is controlled by a first bias signal having a magnitude dependent upon the supply voltage and, in a similar manner, the conductivity of the NMOS bias transistor is controlled by a second bias signal also having a magnitude dependent upon the supply voltage. When the supply voltage exceeds a predetermined level, the first and second bias signals are of respective magnitudes so as to slowly turn on the PMOS and NMOS bias signals. In this manner, the current flow is gradually increased to the sense circuit at high voltages, thereby minimizing noise and power consumption.

Abstract: A switching circuit includes a first switch connected between a first node and a first potential, a second switch connected between the first node and a second potential levels, a third switch connected between the first node and an output terminal, and a fourth switch connected between the output terminal and a third potential. A first control signal controls the conductivity of the first and second switches, a second control signal controls the conductivity of the third switch, and a logical combination the first and second control signals controls the conductivity of the fourth switch.

Abstract: A DRAM includes a data input buffer having a first input terminal coupled to data I/O pins, a second input terminal coupled to a column address buffer, a third input terminal coupled to a column address strobe buffer, and an output terminal coupled to a column decoder. When reading a selected cell of the DRAM, the first row address and the first column address are latched on the falling edge of the row address strobe signal from the address input pins into a row address buffer and from the I/O pins into the data input buffer, respectively, of the DRAM. While the row address is decoded and used to select a row of memory cells of the DRAM, the column address is decoded and used to select one of the cells from the selected row. Data corresponding to the selected cell is forwarded to the I/O pins on the first falling edge of the column address strobe signal.

Abstract: A memory array includes a plurality of columns, each of said columns including a predetermined number of memory cells. A write driver for generating a signal which facilitates the writing of data to one or more of said memory cells is provided and has coupled to an output terminal thereof a write data line. The write data line, along which signals generated by the write driver propagate to selected memory cells, includes a plurality of column nodes. The columns are divided into groups, where each group contains columns bearing consecutive column addresses. One-half the columns in a first group, which bear the first column addresses, are associated with those column nodes closest to the write driver, while the other half of the columns in the first group, which bear the next consecutive column addresses, are associated with the column nodes furthest from the write driver.

Abstract: A nonvolatile memory array is disclosed which includes a plurality of PMOS two-transistor (2T) memory cells. Each 2T cell includes a PMOS floating gate transistor and a PMOS select transistor and is connected between a bit line and a common source line. The select gate and the control gate of each 2T cell in a common row are connected to a word line and to a control gate line, respectively. The 2T cells of the array are programmed using a combination of FN tunneling and BTBT induced hot electron injection, and are erased using FN tunneling. In some embodiments, the array is divided into sectors, where each sector is defined by an n- well region and includes a predetermined number of rows of the 2T cells. Here, the source of each 2T cell in a sector is coupled to a common source line of the sector. In other embodiments, the bit lines of the array are segmented along sector boundaries.

Abstract: A computer processor complex including a hardware processor coupled to a multimedia coprocessor is provided. This computer processor complex is capable of separately processing a stream of non-multimedia instructions in addition to a stream of multimedia instructions such as are used in MPEG audio and video. The computer processor complex includes a visible register set including registers for a program counter and a data pointer. The program counter is used to hold the address in memory where the multimedia instructions are located and the data pointer indicates where the data, corresponding to these multimedia instructions, is located in memory. A hardware processor is coupled to a first bidirectional port on the visible register set and a multimedia coprocessor is coupled to a second bidirectional port on the visible register set. The bidirectional ports allow the hardware processor and the coprocessor to exchange data and status information typically using an interrupt based communication mechanism.

Abstract: A method and apparatus is disclosed which spatially enhances stereo signals without sacrificing compatibility with monophonic receivers. In accordance with one embodiment of the present invention, a stereo enhancement system is implemented using only two op-amps and two capacitors and may be switched between a spacial enhancement mode and a bypass mode. In other embodiments, simplified stereo enhancement systems are realized by constructing one of the output channels as the sum of the other output channel and the input channels. In other embodiments, a pseudo-stereo signal is synthesized and spatially enhanced according to stereo speaker crosstalk cancellation principles. In yet other embodiments, the respective spacial enhancements of monophonic signals and stereo signals are integrally combined into a single system capable of blending, in a continuous manner, the enhancement effects of both.

Abstract: A dielectric layer is formed over an SOI layer and then masked and etched to define a trench. The sidewalls of the trench are thermally oxidized to form a layer of oxide thereon. A polysilicon gate is then formed within the trench. The layer of oxide laterally bounds the gate and thus serves a sidewall spacer for the gate. Dopants are implanted into portions of the SOI layer lying on opposite sides of the trench to form elevated source and drain regions. A layer of silicide such as, for instance, titanium silicide, may then be formed within surface portions of the elevated source and drain. The elevation of the source and drain allows silicon to be sufficiently sourced during formation of the silicide, thereby minimizing agglomeration within the silicide layer. The channel length of a semiconductor device fabricated using present embodiments is controlled by the thickness of the sidewall spacer.

Abstract: A method and apparatus is disclosed which spatially enhances stereo signals without sacrificing compatibility with monophonic receivers. In accordance with one embodiment of the present invention, a stereo enhancement system is implemented using only two op-amps and two capacitors and may be switched between a spacial enhancement mode and a bypass mode. In other embodiments, simplified stereo enhancement systems are realized by constructing one of the output channels as the sum of the other output channel and the input channels. In other embodiments, a pseudo-stereo signal is synthesized and spatially enhanced according to stereo speaker crosstalk cancellation principles. In yet other embodiments, the respective spacial enhancements of monophonic signals and stereo signals are integrally combined into a single system capable of blending, in a continuous manner, the enhancement effects of both.

Abstract: A track and hold circuit is disclosed which may be used in high speed analog to digital conversions. The circuit includes a control transistor which keeps the circuit's input transistor in a conductive state even when the circuit is in hold mode. As a result, the track and hold circuit achieves a high switching speed while minimizing input voltage spikes.