Abstract: An integrated circuit structure comprises a body of semiconductor material and first and second transistors formed in a surface region of the body. The body of semiconductor material comprises a substrate of silicon doped with a p-type impurity and an epitaxial layer of silicon over predetermined surface regions of the substrate. The epitaxial layer is of substantially uniform thickness. Each transistor comprises a base, an emitter and an active collector formed in the epitaxial layer, and a subcollector formed in the substrate and extending beneath the base and the active collector of the transistor. The second transistor comprises, in addition, a contact collector formed in the epitaxial layer and laterally spaced from the base and the emitter of the second transistor.

Abstract: A magnetic latching actuator is disclosed having an arrangement of components which cooperate to minimize internal friction, while ensuring smooth and efficient operation. The invention uses a core having at least one electrical coil. In communication with the core is a permanent magnet. The magnet is positioned against a U-shaped magnetic flux connector having two parallel plates. The plates are sufficiently spaced from each other to permit the passage of a U-shaped armature therebetween. The armature is movable between the plates of the flux connector, enabling the transfer of magnetic flux to the armature while avoiding frictional engagement between the armature and flux connector. The armature further includes two end portions each designed to alternately engage the core at opposite ends.

Abstract: An alkaline, cyanide, aqueous electroplating composition of copper, tin, and zinc includes a small amount of nickel to enhance the inclusion of tin in the copper-tin-zinc plate deposited from the soltion. The plate resists tarnishing by a corrosion test solution, and retains its bright silvery-colored appearance because the plate preferably includes at least about 10.9 atomic wt % tin. The plating method for enhanced tin alloys through nickel additions to the bath is also described.

Abstract: A tristate output circuit includes a pair of transistors having sources connected to a switchable current source and drains separately coupled to a voltage source through separate resistors and switching transistors. When the current source and switching transistors are on, the circuit operates in a back termination mode wherein it amplifies a differential input signal applied across the gates of the transistor pair to produce a differential output signal across their drains for transmission on a transmission line. The load resistors are sized to match the characteristic impedance of a transmission line so as to properly terminate the transmission line. In an open drain mode, the switching transistors are off, uncoupling the drains of the transistor pair from the voltage source so as to increase output impedance. In a tristate mode, the current source and switching transistors are turned off, thereby turning off the transistor pair and rendering the output impedance of the circuit substantially infinite.

Abstract: An output stage for producing a high accuracy differential output signal includes a first differential amplifier providing a pair of single-ended first signals of magnitudes that swing in opposite directions between first and second levels following a change in level of an input signal. A sum of magnitudes of the first signals is controlled by an input control current. The first signals provide input to a second differential amplifier supplying a pair of single-ended second signals swinging in opposite directions between third and fourth levels when the first signals change levels, the second signals forming the differential output signal of the output stage. An indicating signal, provided by the second differential amplifier, supplies a measure of a sum of magnitudes of the second signals. A third differential amplifier produces the control current of magnitude determined by a magnitude difference between the indicating signal and a constant reference signal.

Abstract: A charge-coupled device comprises a substrate of semiconductor material having at least two buried channels formed therein. At least two sets of clock electrodes overlie the buried channels. By application of appropriate potentials to the clock electrodes, an electrical charge may be propagated in controlled fashion along each buried channel towards its output end. A floating diffusion is formed at the output end of each buried channel for receiving charge propagated along the channel. Output transistors are assoicated with the buried channels respectively and each has a control electrode connected to the floating diffusion of the associated channel. An output diffusion is located between the floating diffusions and the control electrodes of the transistors and extends perpendicular to the channels.

Abstract: A method for removably securing the leads of a semiconductor package to the conductive pathways on a circuit board is disclosed. Specifically, a retaining member is provided which includes a plurality of bores each sized to receive a pressure pin. Each pin communicates with a biasing system, enabling the resilient movement of each pin independently of the other pins. The retaining member and pins are positioned above the semiconductor package on the circuit board, and subsequently urged downward so that each pin contacts one of the leads on the package. As a result, the proper pressure is applied to each pin so that it effectively communicates with its designated conductive pathway on the circuit board.

Abstract: The present invention involves a metal alloy heat sink containing tungsten, copper, and nickel. The heat sink is affixed to a ceramic substrate which supports one or more heat-generating electrical components. By adjusting the ratio of tungsten, copper, and nickel, substantial matching of the heat sink CTE with the substrate CTE is possible. Because the CTE of the heat sink is matched with that of the substrate, problems associated with differential thermal expansion are minimized, including micro-cracking and delamination. In addition, the completed heat sink has a relatively high thermal conductivity, and is capable of dissipating substantial amounts of heat.

Abstract: A current source provides an output current whose magnitude is substantially independent of changes in temperature. In each of three embodiments (50, 100, 120), one or more bipolar transistors are employed to provide a compensating current which is dependent on the base-to-emitter voltages, V.sub.BE, of such bipolar transistors. The compensating current changes with temperature so as to offset changes in the uncompensated output current so that the total output current is substantially independent of V.sub.BE. The three embodiments employ current mirror circuits (10, 122) that provide a current source of simple circuit design that is operable with the use of a single power supply at a relatively low voltage.

Abstract: An adjustable support allows a computer terminal or display device to be conveniently positioned above a desk. The support includes a platform for holding the terminal and a pivotally connected linkage assembly comprising proximal and distal arms for vertically and horizontally positioning the platform, the distal arm having the platform mounted thereon. The proximal arm comprises a set of members forming an articulated parallelogram structure, the proximal end of which is rotatable about a vertical post clamped to the desk. The vertical position of the terminal may be adjusted by changing the shape of the articulated parallelogram structure. As the shape of the parallelogram structure changes, the elevation of the distal end of the proximal arm changes which in turn affects the vertical position of the platform and display device.

Abstract: A platform supporting an electronic device above a work surface, the platform being mounted on a carrier or trolley that is movable between two or more work stations on an elongate base having a track on which the trolley travels. The platform is attached to the trolley by a mounting head that provides tilt and rotation of the platform, and the height of the base above the work surface is adjustable.

Abstract: A frequency-compensated transistor feedback amplifier provides relatively wide bandwidth and relatively large phase and gain margins, irrespective of the transconductance of the transistors in the amplifier. Each one of three preferred embodiments (10, 50, 104) of the invention includes a transconductance stage (20, 68, 68) and an amplifier stage (12 and 14, 54, 54 and 14). The transconductance stage delivers an input signal to the amplifier stage, which produces an amplified replica of the input signal. A feedback capacitor (24, 88, 24 and 88) connected between the output and the input of the amplifier stage provides dominant pole compensation by which the magnitude of the loop gain diminishes by 6 dB/octave with increasing frequency. The capacitor provides a forward feedthrough path for any residual portion of the input signal so that the residual portion arrives at the output of the amplifier stage in substantially the same phase relation with that of the output signal of intermediate frequency.

Abstract: A digital-to-analog converter circuit (10) comprises a current switch (22) that has differential input conductors (16a, 16b, . . . , 16n and 18a, 18b, . . . , 18n) which receive complementary logic voltage signals corresponding to a digital input word (X.sub.1, X.sub.2, . . . , X.sub.n). The current switch synthesizes an output signal (V.sub.o -V.sub.o) whose magnitude corresponds to the weighted value of the digital input word. The circuit further comprises a current reference source (60) that develops a reference current (I.sub.REF) from which transistor constant-current sources (48a, 48b, . . . , 48n) in the current switch derive binary-weighted currents to synthesize the output voltage signal. The current reference source includes an impedance element or resistor (70) through which the reference current flows and which is scaled to the load impedance connected to the current switch.

Abstract: A current mirror includes first and second transistors having interconnected bases and having emitters respectively coupled through first and second resistors to a common potential source. A collector voltage of the first transistor is fed back to the transistor bases through a feedback capacitor, and through a unity gain amplifier and series resistor, to form a feedback loop for controlling the voltage at the transistor bases. A current source connected to the collector of the first transistor causes the second transistor to produce an output collector current substantially equal in magnitude to the input current. To prevent circuit instability, the feedback capacitor and the aforementioned series resistor are sized to reduce the frequency at which the open loop gain of the feedback loop is unity so that it does not exceed the short-circuit current gain-bandwidth product of the first transistor.

Abstract: A high-speed, supply independent level shifter is implemented in bipolar, JFET, MOSFET or MESFET integrated circuit technology. A level shift circuit having a desired input potential V.sub.1 and a required output potential V.sub.2, is incorporated into a first current leg connected between first and second supply voltages. A second current leg in parallel with the first leg establishes a reference current. The two current legs are coupled by a current mirror to establish a fixed, preferably equal, relationship between the currents in the two legs. Each current leg includes a reference resistor. A buffered, floating voltage source is coupled in series with the resistor in the first leg to the control conductor of the current mirror. The voltage source is designed and the resistor values selected to provide a potential V.sub.3 that is an additive function of potentials V.sub.1 and V.sub.2 such that V.sub.1 is independent of the supply voltages.

Abstract: A method of electrolytic deposition of metal is used to decrease the minimum size pattern that can be obtained using photolithography. In the manufacture of integrated circuits, a layer of metal and then photoresist is deposited on the dielectric layer of the substrate prior to masking to define the gate apertures. After masking and etching through to the dielectric, metal is electrodeposited on the metal edges that abut the gate aperture, thus decreasing the aperture size. After that decreased gate dimension is etched into the dielectric to define the gate lengths of the semiconductor devices, the wafer is stripped and the subsequent manufacture proceeds in the conventional manner.

Abstract: In an integrated circuit, a reference voltage proportional to the pinchoff voltage of a field effect transistor is created by providing a current source, including a first depletion-mode FET, and a second depletion mode FET having a source connected to the drain of the first FET at an output node. The first and second FETs have their source and drain, respectively, connected to the first and second supply voltages, respectively, so that in operation, substantially equal currents flow through the two transistors. The FETs are biased to operate in saturation. Regarding the first FET, this current is equal to I.sub.DSS (defined as I.sub.D when V.sub.GS =0) of the first FET (I.sub.DSS1) and is not greater than, and usually less than, I.sub.DSS of the second FET (I.sub.DSS2). The dimensions of the FETs are proportioned such that the gate-source voltage across the second FET substantially equals a constant times the pinchoff voltage.

Abstract: An apparatus for controlling the pressure exerted on a probe in an integrated circuit testing station is disclosed. The apparatus is mounted to a support structure within the station directly above the probe. The testing station further includes a motorized lift system for moving an integrated circuit upward against the probe for testing. The invention uses a pressure pad positioned directly above the probe which is attached to the support structure using a resilient member. Associated with the pad is an electrical contact system connected to the lift system. As the lift system moves the circuit upward, it contacts the probe which pushes against the pad. Movement of the probe and circuit against the pad permits secure engagement of the probe with the circuit. As the circuit continues to move upward, the pad is urged upward, causing the electrical contact system to deactivate the lift system before damage to the probe occurs.

Abstract: A dense, sintered ceramic material having a low dielectric constant and a low coefficient of thermal expansion is provided from a mixture of 10-50 wt. % alumina, 0-30 wt. % fused silica, and 50-60 wt. % of a frit comprised of CaO, MgO, Al.sub.2 O.sub.3, B.sub.2 O.sub.3, and SiO.sub.2. The mixture has a minimum sintering temperature in the range of 850.degree.-1000.degree. C., and can be formed by conventional manufacturing techniques. It is particularly useful for the fabrication of single or multilayer electronic circuit substrates.

Abstract: A probe mount carries a probe with test points having ends in a test point plane. The probe mount is supported at three spaced apart locations by respective first, second and third supports, each adjacent to a respective one of the test points. These probe supports permit independent shifting of each of the three locations along respective parallel lines. As these locations are shifted relative to one another, the test point plane is tilted until it is parallel to a second plane containing the surface of an integrated circuit wafer to be probed. A test surface is positioned in the second plane and advanced toward the probe. As the test points contact the test surface, the test point plane is tilted. Microprocessor controlled stepper motors may be used to tilt the test point plane and to shift the test surface.