Abstract: A charge-coupled device package comprises a substrate of dielectric material and a charge-coupled device die mounted on one main face of the substrate. The substrate is placed in heat exchange relationship with a cold sink, such as a bath of LN.sub.2. A temperature sensor senses the temperature at a location on the main face that is in close proximity ot the die. A film resistor is adhered to the opposite main face of the substrate and receives a current that depends upon the temperature sensed by the sensor.

Abstract: A method for determining the thermal characteristics of a semiconductor packaging system is provided which uses a platinum resistor test unit. The platinum resistor is preferably sized to approximate the dimensions of the semiconductor device for which the package was designed, and is installed within the package. The packaged resistor is then thermally calibrated at a plurality of temperature levels to generate a linear temperature versus resistance graph or equation corresponding thereto. Next, voltage is applied to the packaged resistor causing such resistor to "self heat." Its resistance is calculated, and the temperature corresponding thereto is obtained from the graph or equation. Such temperature is the surface temperature of the resistor. This temperature may then be used to calculate the temperature gradient from the inside of the package to any reference point on or near the outside of the package, the temperature of which has been previously determined.

Abstract: A viscoelastic and ink-immiscible fluid is used to form a membrane over the ink orifice of a drop-on-demand, pressure pulse ink jet head. The membrane lies in a plane perpendicular to the direction of emission of ink drops, and provides a barrier between the ink orifice and the external atmosphere. Evaporation of the ink, or entry of contaminants including air into the ink, is thus inhibited. The elimination of evaporative clogging then permits the use of a smaller orifice. Wetting of the exterior surface of the ink jet head by the flow of ink through the ink orifice is also inhibited, thus making possible the production of more uniform ink drops that will emerge in a constant direction. The elastic property of the membrane permits the passage of an ink drop therethrough, followed by the closing up of the membrane.

Abstract: A combined digital-to-analog converter and latch memory circuit (10) includes an R-2R resistive ladder network (12) and a current-controlled latch memory 18. The R-2R resistive ladder network has plural input nodes (100 and 102) and an analog signal output (104). Each of the input nodes corresponds to a different bit of a digital word that is to be converted to an analog signal. The current-controlled latch memory includes plural subcircuits (14 and 16). Each of the latch subcircuits uses an amount of current to store the logic state of the bit of the digital word and to derive directly the node of the R-2R resistive ladder network. This configuration promotes the efficient use of space, power, and circuit elements.

Abstract: A multi-layer metallization method and structure that permits the use of sodium-ion contaminated titanium-tungsten (Ti:W) as a barrier metal with gold conductor metal on a silicon substrate, without significant degradation of device characteristics. After depositing the barrier and conductor metal layers, a layer of phosphorous-silicate glass (PSG) is anisotropically-etched to expose the field oxide and top surface of the conductor metal but leave PSG layer on each sidewall of the metallization structure. The circuit is then annealed at 400.degree. C. for 30 minutes. Then, an adhesion layer (Si.sub.3 N.sub.4) and an insulative layer (SiO.sub.2) are deposited over the metallization structure and field oxide, with the adhesion layer in contact with the top surface of the conductor metal and the gettering composition.

Abstract: A twisted nematic liquid crystal material used in a dual-frequency addressable liquid crystal cell is disclosed. Specific materials include an eutectic mixture of 2-5 monoester compounds having the formula R--X--Y--CO.sub.2 --Z--R', wherein R and R' is a straight alkyl having 2-7 carbon atoms and where each of X, Y and Z is a phenyl or trans-cyclohexyl and at least one of X, Y and Z is a trans-cyclohexyl. Also included are up to 25 weight percent of dopants to reduce viscosity and up to 10 weight percent of additives to lower the cross-over frequency, the additives being of the formula: ##STR1## wherein X is selected from the group consisting of: ##STR2## wherein R is a straight alkyl having 2-7 carbon atoms.

Abstract: A single phase, buried channel charge coupled device has a high conductivity layer overlying the pinned regions thereof and extending to the channel stop regions, thereby facilitating the transfer of charge carriers between the channel stop regions and the pinned regions in order that the potential profile underlying said pinned regions may be more readily maintained. Extension of that high conductivity layer over the channel gate electrodes also facilitates the transmission of clocking voltages to the channel gate electrodes and allows the device to operate with decreased power losses.

Abstract: An electro-optical transducer module comprises a base member having a generally flat surface and a platform upstanding from the flat surface, an electro-optical transducer mounted on the platform, a fiber mount plate secured to the base member with one main face in confronting relationship with the generally flat surface of the base member, and an optical fiber secured to the fiber mount plate by way of its other main face. The optical fiber has an end face that is in optically-coupled relationship with the electro-optical transducer.

Abstract: An integrated logic circuit comprises a direct coupled FET logic input stage and a super buffer logic output stage. The input stage comprises a depletion-mode FET having its drain connected to a first reference potential level and having its gate and source connected together, and a first enhancement mode FET structure having its drain connected to the source of the depletion-mode FET, its source connected to a second, lower reference potential level and having at least one gate connected to receive an input logical signal. The super buffer logic output stage comprises a second enhancement mode FET structure that is essentially identical to the first enhancement mode FET structure, the source of the second enhancement mode FET structure being connected to the second reference potential level and the gate of the second enhancement mode FET structure being connected to the gate of the first enhancement mode FET structure.

Abstract: A voltage reference circuit (10) for a constant-current source transistor (16) of the bipolar type provides an output voltage in two components. The first voltage component varies in accordance with the negative temperature coefficient (C.sub.1) of the base (58)-emitter (78) junction of a bipolar transistor (60) to compensate for temperature-related changes in the base (18)-to-emitter (22) voltage of the constant current source transistor. The second voltage component is of fixed magnitude and develops collector current (I.sub.0) flow through the transistor and thereby actuates constant-current source operation. The result is a transistor constant-current source that provides a constant output current independent of temperature.

Abstract: The source and drain of a first depletion-mode MESFET (DFET) define the controlled current path of a switch, the switch being open or closed depending on whether the gate-to-source voltage (V.sub.gs) for the first DFET is greater or less than the pinch-off voltage (V.sub.p) for the first DFET. The first DFET has its gate connected to a first circuit node. A second DFET, connected as a source follower, has its gate connected to the source of the first DFET. A first diode has its anode connected to the first circuit node and its cathode connected to a second circuit node. A second diode has its cathode connected to the second circuit node and its a node connected to the source of the second DFET. At least one additional diode is connected anti-parallel to the first diode between the first and second nodes.

Abstract: A new and efficient method for attaching an optical fiber to a substrate to form a structurally secure optical fiber package is disclosed. The method first involves coating an optical fiber with an external layer of gold. A silicon retaining member is then provided having a groove therein sized to retain and receive the coated optical fiber. The silicon retaining member and optical fiber are then positioned on a substrate preferably constructed of alumina. Deposited on the substrate is at least one metal pad having an external gold layer on which the silicon retaining member is placed. The optical fiber, silicon retaining member, and substrate are then heated at a temperature sufficient to form a silicon/gold eutectic alloy between th silicon of the retaining member and the gold layers of the optical fiber and pad. Such heating involves a temperature of at least 370.degree. C. Heating is preferably accomplished using a resistor secured to the underside of the substrate.

Abstract: A current source utilizes N+1 transistors to produce N output currents of magnitudes proportional to a variable reference current. Each transistor emitter is resistively coupled to a common potential and each transistor base is driven by a common control voltage, offset by a separately adjustable amount for each transistor. The control voltage is produced by an amplifier having a grounded inverting input and a non-inverting input coupled to the collector of a first of the transistors and resistively coupled to a variable reference voltage source. The reference voltage source is adjusted to produce a desired reference current in the collector of the first transistor and the magnitude ratio of an output current produced in the collector of each of the N remaining transistors to the reference current is controlled by adjusting the ratio of emitter resistance of the first transistor to the emitter resistance of the remanining transistors.

Abstract: A circuit for converting an input logic signal to an output logic signal having differing high and/or low logic voltage levels includes an output transistor and a load resistor coupling a collector of the output transistor to a supply voltage. The emitter of the output transistor is grounded. An input stage clamps a base of the output transistor to ground when the input signal voltage level is low, thereby turning the output transistor off and allowing the load resistor to pull the output signal, produced at the output transistor collector, up to its high logic level. When the input signal is high, the input stage unclamps the base of the output transistor from ground and a feedback stage responsive to the output signal supplies feedback current to the base of the output transistor, which feedback current increases with the magnitude of the output logic signal. The feedback current turns on the transistor, thereby increasing load current through the load resistor so as to reduce the output signal level.

Abstract: In a GaAs integrated circuit, a voltage reference generator includes a pair of Schottky diodes and a first, current-source connected, depletion-mode MESFET coupled in series to conduct current from a ground node to a voltage supply node. The current-source connected FET causes a constant current to flow from the ground node through the diodes, producing a constant voltage drop which generates a constant reference voltage at a reference node between the diodes and FET. A second pair of Schottky diodes is connected in series between the source of the FET and the voltage supply node, in a loop coupling the source to the gate of the FET, to provide a voltage difference Vgs across the FET proportional to voltage drop across the second pair of diodes. This voltage difference varies with fabrication process and temperature variations and causes the first FET to modify the amount of current flow to compensate so as to maintain a constant voltage drop across the first pair of diodes.

Abstract: A self aligned, nonoverlapping gate structure for a charge coupled device is fabricated by depositing three sets of interleaved polysilicon gate electrodes. The first set of electrodes is applied in a planar form and sized to a width of about one-third the spacing of the electrodes of the first set. The second and third sets of electrodes are applied to overlap, in turn, portions of the previously applied electrodes. A thick shield layer of SiO.sub.2 is deposited and patterned atop the first and second sets of gate electrodes. After deposition of the third set of electrodes, the shield layers are removed to provide passageways extending beneath the overlapping portions of the second and third sets of electrodes. Such overlapping portions are then removed by etching through the passageways, to produce a nonoverlapping, generally planar gate structure.

Abstract: A pressure sensing apparatus for use in an integrated circuit testing station is disclosed. The testing station includes a probe, a support structure, and lift means for moving an integrated circuit upward toward the probe. The invention specifically consists of a pressure pad secured to the support structure directly above the probe. The pad includes a resilient body portion having a rigid tip. Embedded within the pad is a piezoelectric element having electrical contact leads attached thereto. When the testing station is used, an integrated circuit is moved upward by the lift means toward the probe. As the circuit contacts the probe, it moves the probe upward. As the probe moves upward, it pushes on the pad, causing internal pressures to be generated therein. Such pressures are transmitted to the piezoelectric element which generates electrical impulses proportional to the pressures exerted on the pad.

Abstract: An electronic probe assembly provides previously recorded data as to probe identification and optimum compensation tuning of the probe to a connected "intelligent" test and measurement device so that proper test procedures may be confirmed, either by display of such data or by the generation of error messages.

Abstract: An integrated circuit gate process and structure are disclosed which provide a self-aligned, recessed gate enhancement-mode GaAsFET. The process includes making self-aligned implants prior to gate metallization, with an intermediate step of applying patches of plasma- and chemical-etch resistant dielectric, such as zirconium oxide (ZrO), over the self-aligned implants to fixedly define gate length. The self-aligned gate process includes stair-stepping three successive implants, in respect to both depth and concentration, to provide a dopant concentration gradient inclined depthwise away from each side of the gate. The self-aligned, recessed gate GaAsFET exhibits improved source-gate resistance without degradation of gate-drain capacitance, increased gain and drain-source current, and reduced knee-voltage. Gate length is minimized to the limits of photolithography without degrading input resistance.

Abstract: An optical switching device selectively couples an optical port of a first type (e.g., an input port, at which a light beam is introduced into the apparatus) to one of at least two optical ports of a second type (e.g. output ports, from which a light beam leaves the apparatus) which are at predetermined, angularly-spaced positions about a central axis of the device. The device comprises an optical imaging device mounted to rotate about the central axis between a first position, in which the port of the first type is optically conjugate with one of the ports of the second type, and a second position, in which the port of the first type is optically conjugate with the other port of the second type.