Abstract: An integrated circuit package comprises an integrated circuit chip and a flexible sheet-form interconnect member that comprises dielectric material and conductor runs supported by the dielectric material in mutually-insulated relationship and having termination points arranged at the main face of the interconnect member in a pattern that corresponds with the pattern of contact pads on the interconnect face of the chip. The chip and the interconnect member are adhesively bonded together by means of a material that is interposed between the main face of the interconnect member and the interconnect face of the chip, but is not interposed between the contact pads and the termination points, and adheres to both the interconnect member and the chip.

Abstract: A self-aligned gate GaAsFET fabrication process and structure are disclosed in which the gate metallization is offset to one side of the channel aligned with the source-side implant. The arrangement is advantageously provided by a photolithographic fabrication process in which a pair of self-aligned implants are made, before gate metallization. As an intermediate step, a first etch-resistant ZrO patch is deposited over at least one of the self-aligned implants aligned therewith. Then, a second such patch is deposited which overlaps the other self-aligned implant and extend a distance over the channel between the two implants. The first and second patches are thereby spaced closer together (e.g., 0.5 .mu.m) than the implants (e.g., 1.0 .mu.m). The patches fix the gate length at less than implant spacing and offset the gate metallization along the source-side self-aligned implant, away from the drain implant. The gate is preferably recessed.

Abstract: A stepping motor generates first and second voltages each varying in accordance with a sinusoidal function having a period proportional to the period of rotation of the motor's rotor, the first and second voltages being in quadrature with each other. A control device generates from the first and second voltages a signal representative of a number that is proportional to the square root of the sum of the squares of the first and second voltages. This signal is used to modify the energizing current provided to the phase windings of the stator, in order to reduce fluctuations in torque and shaft angular velocity.

Abstract: A comparator includes a source degenerated latching differential amplifier and an input differential amplifier interconnected in stacked fashion and connected with the input amplifier having inverting and non-inverting outputs coupled respectively for positive feedback to the inverting and non-inverting inputs of the latching amplifier. Means are provided to limit the relative difference between the signals at the inverting and non-inverting inputs to the latching amplifier so that when the latching amplifier is activated a minimum current will always be present in both sides of the samplifier. Means are provided to selectively apply or not apply a common bias current to the latching amplifier such that on application thereof, the positive feedback from the input amplifier outputs causes the latching amplifier to drive the highest input amplifier output to a high voltage level limit and to drive the lowest input amplifier output to a low voltage level limit.

Abstract: An integrated circuit package comprises at least two integrated circuit chips each having a plurality of contact pads arranged in a first pattern on the interconnect face of the chip, and an elastic sheet-form interconnect member. The interconnect member has at least two main face areas, associated with the chips respectively, and comprises dielectric material and conductor runs supported by the dielectric material in mutually electrically insulated relationship and having termination points arranged in at least two second patterns at the main face areas respectively and corresponding with the first patterns respectively. The interconnect face of each is in confronting relationship with the associated main face area of the interconnect member, and the contact pads of the chip and the termination points of the associated main face area are in mutually registering relationship. A metallurgical bond is formed between each contact pad and the corresponding termination point.

Abstract: A microprocessor-based apparatus for testing the electrical condition of electronic circuitry, particularly computers, employs a buffer and a latch associated with each of the address bus and the data bus to provide electrical isolation of said buses. In using the apparatus, the integrity of a central testing "kernel" comprising the testing program itself with its testing data in ROM is first verified. The testing program then evaluates, in order, the data bus, the address bus, and then such additional and addressable circuitry as may be connected to said data bus and address bus. Incorporation of analog-to-digital converters permits determination of actual circuit node voltages, in addition to digital levels or the presence of open or short circuits.

Abstract: A Schottky barrier diode is made from a substrate of semiconductor material by forming, on a major surface of the wafer, a layer of dielectric material defining a restricted opening through which the semiconductor material is exposed. A metal which forms with the semiconductor material a single phase compound which is inherently stable at temperatures up to 600 deg. C. is deposited into the opening, into contact with the exposed semiconductor material. By heating the substrate and the metal deposited thereon, the metal reacts with the semiconductor material to form a body of the single phase compound. A layer of refractory metal which reacts with the dielectric material is deposited over the dielectric material and the body of single phase compound.

Abstract: First and second transistors are connected as a differential pair, and a third, current source transistor has its collector connected to the emitters of the first and second transistors and draws a first constant current. Fourth and fifth transistors are connected as a second differential pair with the collectors of the fourth and fifth transistors connected to the collectors of the first and second transistors respectively and with the bases of the fourth and fifth transistors connected to the bases of the second and first transistors respectively. A sixth, current source transistor has its collector connected to the emitters of the fourth and fifth transistors and draws a second constant current that is much smaller than the first constant current. All four transistors of the two differential pairs are essentially identical, and the two current source transistors have the same parasitic capacitances.

Abstract: A gallium arsenide differential amplifier is compensated against temperature and process induced variations so as to provide phase and amplitude matched differential output signals centered about an internal GaAs reference voltage. Compensation of the amplifier is effected by one or more current sources which are adjustably responsive to the dynamic common mode level of the output signals. The resultant amplifier provides a high common mode rejection ratio and facilitates implementation of otherwise impracticable differential GaAs circuit topologies.

Abstract: Field effect transistors are manufactured using a substrate of compound semiconductor material by defining two gate areas which have their longitudinal dimensions so oriented with respect to the crystal axes of the substrate that the substrate material is more readily etchable through one of the gate areas than through the other gate area. The semiconductor material is etched through both the gate areas simultaneously with the same etchant, whereby gate recesses of different respective depths are formed in the substrate. Metal is deposited into the recesses.