Abstract: In a digital processing unit having a plurality of digital signal processors, a first digital signal processor can request a direct transfer of a signal group stored in the memory unit of a second digital signal processor. In order to insure that the second digital signal is active, a control signal is generated by the direct memory access controller of the first digital signal processor. The control signal is applied the directly to the memory access controller of the second digital signal processor. When the second digital signal processor is in an IDLE mode, the control signal activates the second digital signal processor.

Abstract: The invention relates to a software system and method for configuring a software system for interaction with a hardware system. In this method, the software system (140) is executed on a host processor interconnected with the hardware system (103). A database (152) is accessed to obtain a description of a set of functional components present within the hardware system (103). A software representation (154) of the capabilities of each functional component is created by using the description of the set of functional components. Then, the software representation (154) is interrogated to determine a set of operational capabilities of the hardware system (103). The software system (140) is then operated in a manner that is responsive to the set of operational capabilities of the hardware system (103).

Abstract: An inter-module communication system provides for the exchange of status/event signals between interface modules monitoring the activity of external apparatus. The communication system includes a dedicated inter-modular control unit that collects status/event signals from the modules and an inter-modular control bus for distributing the status/event signals to the other modules. The status/event signals are applied to a multiplexer. The multiplexer can be programmed to transmit specified status/event signals. The specified status/event signals provide inter-modular coordination among the plurality of the modules without involvement of the device peripheral bus.

Abstract: An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation file having translation elements corresponding to translation of said identified source elements (86) and having an interface (16) for receiving inputs for modifying said translation.

Abstract: A user interface that allows a user to visually understand, inspect, and manipulate a compiled application program as a function of compiler options, such as, code size and speed, is provided.

Abstract: In order to sort signal group elements organized in blocks in a time-division multiplex protocol into frames of related elements, an address unit addresses the first element in each of the element blocks, then the second element in each element block, etc until all of the elements of all of the blocks have been addressed. In this manner, the related elements are sorted into frames of elements. The address unit performs this element sorting using a base address, an element index equal to the number of elements in a block, and a frame index equal to {the number of elements times (the number of frames minus one)} minus one as parameters.

Abstract: In a Flash memory unit, the storage of a logic signal in the memory cells is determined by performing a READ operation. The NORMAL READ operation requires that the floating gate store an amount of charge QNR above which a logic “0” is identified and below which a logic “1” is identified as being stored in the memory cell. A second level of charge QTR stored on the floating gate is used in a TEST READ operation. The stored charge QTR is greater than the stored charge QNR, but less than the charge stored on the floating gate as the result of a WRITE operation. The result of a TEST READ operation is compared with a NORMAL READ operation of a memory cell. When the logic state identified by the TEST READ operation and the NORMAL READ operation are not the same, the charge on the cell is determined to have decayed below a prescribed level and the memory cell is refreshed to the level that is present during a WRITE operation.

Abstract: In a digital signal processing unit, addressing apparatus implements a multiplicity of addressing modes. The addressing modes include a circular buffer memory mode, a frame mode, and a sorting mode. To increase the speed of the address modification, the index, the index in the presence of a positive wrap-around, and the index in the presence of negative wrap-around are determined together. Other apparatus determines the addressing mode and provides control signals for the selection of the correct index. The correct index is combined with the base address to provide the next new address.

Abstract: A microprocessor and method for operating this microprocessor are disclosed. The microprocessor contains multiple execution units that receive instructions from an instruction pipeline. A loop cache memory is connected in communication with the instruction pipeline, such that it may both store instructions from the instruction pipeline and issue instructions to be executed by the execution units. A loop cache controller controls instruction flow. In operation, the loop cache controller is preferably signaled by a software instruction to begin building a software pipelined loop of a specified size into the loop cache memory. The loop cache controller then begins accumulating instructions from the instruction pipeline into the loop cache memory; these instructions may also remain in the pipeline for execution. When the kernel of the software pipelined loop is built into the loop cache memory, the controller preferably stalls the instruction pipeline and executes the loop using the cached instructions.

Abstract: An improved microprocessor is provided having a program control unit for storing and then decoding instructions, a program address generation unit for generating addresses used to obtain instructions, an address register arithmetic unit for generating addresses for data, an arithmetic logic unit for performing operations on data, a shifter unit for shifting data in response to a predetermined instruction, a multiplier unit for performing multiplication of two input values; and a plurality of registers of which at least a portion are individually selectively associated with one or more of said units as a function of an instruction.

Abstract: An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation file having translation elements corresponding to translation of said identified source elements (86) and having an interface (16) for receiving inputs for modifying said translation.

Abstract: In order to provide communication between two processors in a data processing system, a target processor includes apparatus that can store data signal groups from a source processor. Having stored a data signal group from the source processor, the target processor notifies the source processor of the receipt of the data signal group. In response to the presence of the stored data signal group, the target processor executes a interprocessor command or instruction identified by the transferred data signal group. The source processor at a preselected time, executes an instruction to determine if the command designated by the data signal group stored in the target processor has been executed. The commands specified by the transferred data signal groups can be executed under hardware control by the target processor in a relatively short time immediately following completion of the instruction in execution in the target processor at the time of the transfer of the data signal group.

Abstract: In a dynamic random access memory unit, a parity check logic circuit includes a parity signal generating circuit which generates a parity signal for each signal group transmitted on the input/output data bus. For a sequence of data groups on the data bus, a parity signal for each data group is generated, the parity signal combined with a parity signal generated for the previous data group or data groups. For a read operations, a parity signal is generated for each of sequence of retrieved data groups and combined with the parity signal(s) of the previous data groups of the sequence. The resulting parity signal is compared with the parity signal associated with the data group sequence and stored in the memory unit to generate a flag signal when the parity signals are not identical. For a write operation, the resulting parity signal for all the data groups is stored in memory unit at a location associated with the sequence of data groups.

Abstract: In a dynamic random access memory unit, the voltage difference between bitline pairs, resulting from the transfer of charge between the bitline pair and a memory array (5.sub.L), is amplified by an associated sense amplifier unit (10.sub.L). A multiplicity of sense amplifier units (10.sub.1 -10.sub.M) are activated by a sense amplifier driver circuit. (16, 18, 15 and 17) in typical operation. During a first period of time, a first transistor circuit (15 and 17) of the sense amplifier driver unit capable of providing a limited amount of charging current, activates the sense amplifier units (10.sub.1 -10.sub.M). During a second period of time, the first transistor unit (15 and 17) and a second larger transistor unit (16, 18) activate the sense amplifier units. In order to provide a more effective activation during the first period, function of the first transistor circuit (15, 17) is performed by a plurality of transistor circuits (15.sub.1 -15.sub.L, 17.sub.1 -17.sub.

Abstract: In an integrated circuit, gate electrode stack of which is subjected to self-alignment processes, the sheet resistance is lowered by including a tungsten layer 15. The tungsten layer 14 is protected by a sidewall material 21 of SiN.sub.x or SiO.sub.2 after an etching step which did not extend to the substrate 11. During a subsequent etching step in which the stack extends to the substrate 11, the sidewall material 31 acts as a hard mask protecting the upper portion of the stack. After the lower portion of the stack is protected by a re-oxidation layer 41, the entire stack can be processed further without deterioration of the sheet resistance of the tungsten layer 15.

Abstract: A technique for providing a design window for scaled technologies in which good electrostatic discharge/electrical over stress damage and optimum transistor operation can be achieved without the use of additional masks or design steps. The M, beta, and R.sub.sub parameters of the NMOS transistor 13 and associated parasitic npn transistor 10 are selected to provide the design window.

Abstract: In a dynamic random access memory device, the time required for implementation of memory cell data retention time testing procedures can be reduced by changing the voltage level(s) applied to the components of the storage cell when compared to the voltages applied during the typical memory cell operation. By changing the voltage(s) applied to the components, the difference in the bitlines detected by the sense amplifier will be reduced. Because to the reduced bitline voltage difference, the decay of the charge on the storage cell causes a reduction in the data retention time. The data retention time is reduced in manner related to the typical memory cell operation. The altered voltage(s) can be applied to the storage cell bitlines and/or to the storage cell dummy capacitances.

Abstract: An integrated circuit memory device (21) includes plural input/output pins (30, 127 and others) and plural arrays of addressable storage cells (31-46). A set of circuits (51, 68, 70, 71-86, 90) provides access to a unique storage location in each array (31-46) through a given row and column address. A writing circuit (47, 68, 70, 71-86, 91-106, 131-146), designed for test, provides in parallel plural copies of a test data bit. The test data bit is applied through a single pin (30) and a common data-in lead (68), for storage in an addressed storage cell in each of the arrays. A readout circuit (110, 111, 112, 171, 127, 201-216, 131-146) is arranged for reading out the stored test data bit from the addressed storage cell in each of the arrays (31-46). The writing circuit, while in a block write test mode, stores the test data bit on the common data-in lead (68) in a block of address locations in each array (31-46).

Abstract: In a dynamic random access memory device, the time required for implementation of memory cell data retention time testing procedures can be reduced by changing the voltage level(s) applied to the components of the storage cell when compared to the voltages applied during the typical memory cell operation. By changing the voltage(s) applied to the components, the difference in the bitlines detected by the sense amplifier will be reduced. Because to the reduced bitline voltage difference, the decay of the charge on the storage cell causes a reduction in the data retention time. The data retention time is reduced in manner related to the typical memory cell operation. The altered voltage(s) can be applied to the storage cell bitlines and/or to the storage cell dummy capacitances.

Abstract: A smart memory (10) is provided that includes data storage (12 and 18) and a processing core (14 and 16) for executing instructions stored in the data storage area (12 and 18). Externally, smart memory (10) is directly accessible as a standard memory device. In a first mode of operation, the smart memory (10) is a data storage facility for an associated central processing unit (22). In a second mode of operation, the smart memory (10) is a storage facility for the processing core (14 and 16) and for central processing unit (22) for simultaneous execution of instructions. The central processing unit (22) controls the mode of operation and determines the instructions executed by the processing core (14 and 16). The wide data bus, available with an integrated processor/storage facility, permits certain processing operations to be off-loaded to the smart memory (10) where the processing operations can be performed more efficiently.