Abstract: An integrated circuit interconnect structure is provided, along with a method of forming the integrated circuit interconnect structure. A semiconductor material layer has an elongate trench formed therein. A conducting region is disposed in the trench. An insulator region overlies the conducting region. One or more contact regions are disposed through the insulator region to contact the conducting region.

Abstract: A dynamic random access memory part 30 provides a write per bit feature by locating the respective write mask information latches 118 adjacent the respective local I/O buffers 116. The write mask information thus passes through the data latch 108 and across the data path to the local I/O buffer 116 before being latched. This reduces the area otherwise needed for the additional write mask lead, which in a x8, x16, x32 or x64 bit part can be intolerably large.

Abstract: The plate voltage for a Dynamic Random Access Memory storage cell array is provided by two amplifiers. The first amplifier operates at a relatively low power level and compensates for leakage in the storage cell array, the compensation initiated by a departure of the plate from a nominal value which exceeds a preselected amount. The second amplifier operates at a higher power level and provides compensation for transients in the plate voltage resulting from the charging and discharging of the storage cells. Because the transients occur when the storage cells are accessed, the second amplifier is enabled only when a group of storage cells is accessed. In addition to operating at a higher power level, the second amplifier is more sensitive and responds to smaller excursions from the nominal voltage. Both the first and the second amplifiers have separate driver circuits for responding to excursions above and for responding to excursions below the nominal voltage.

Abstract: A read/write memory is disclosed, which has the capability of writing the same data state to multiple memory cells in a selected row in a single cycle. The invention is incorporated into the memory by a capacitor which is selectively connected to one of the bit lines received by each sense amplifier to override the sensing operation, thereby setting the polarity of the sensed differential voltage to a predetermined state. The restoring operation of the sense amplifier restores the sensed data state into the selected memory cell, completing the write. The capacitor may be connectable to multiple bit lines, for efficiency of design. Each capacitor has sufficient capacitance to fully discharge a stored "1" value plus the dummy capacitor charge, for each of the bit lines to which it will be connected. Logic is incorporated into the memory to receive the data state to be written, and to receive the least significant bit of the row address.

Abstract: In a dynamic random access memory in which the number of data buffers is selectable, a buffer supply can be configured by a control signal to provide pump charge capacitance which is appropriate for providing the power required for energizing the selected number of buffers. In response to an external control signal, a second capacitor (or capacitor bank) can be precharged and then applied to the output terminal of buffer supply simultaneously with the precharging and application of the charge on the first capacitor. The dimension of the first capacitor is suitable for a buffer supply for the first buffer configuration and the second capacitor is suitable for a buffer supply for additional buffer amplifiers of the second configuration.

Abstract: The invention provides an apparatus (10) for encasing a printed wiring board (12). Apparatus (10) comprises a substantially tubular housing (14) having internal ribs (30) formed along first and second sides (32) and (34) of housing (14). Printed wiring board (12) is received in housing (14) and maintained in place by ribs (30). An end cap (18) having an aligning member (36) is placed in a first opening (22) of housing (14). A coupling member (20) comprising a connector (40) and a support shell (42) is inserted into a second opening (28) of housing (14).

Abstract: The invention discloses a high density semiconductor package. In one embodiment, two semiconductor chips are each affixed on a corresponding one of two lead frames. The semiconductor chips and the lead frames are encapsulated, wherein only a portion of the leads of the lead frames protrudes and extends from the package.

Abstract: An MOS DRAM memory device includes an output buffer having an N-channel output transistor that must receive a boosted gate signal to produce a full Vdd output high logic level signal at the output terminal. The N-channel transistor connects between the Vdd supply voltage and the output terminal. The output buffer connects a Vdd supply voltage to the gate of the output transistor for a short period sufficient to raise the gate to the Vdd voltage level and then disconnects the Vdd supply. The buffer then connects a Vdd+ supply voltage to the gate to increase the gate voltage at least one transistor threshold value above the Vdd supply voltage. This provides the Vdd voltage at the output terminal.

Abstract: A method and apparatus for testing the self-refresh operation of a dynamic memory part are provided in which an oscillator (140) is coupled to a self-refresh counter (142). The self-refresh counter (142) causes a refresh row address counter (144) to generate row addresses for self-refresh cycles. The refresh row address counter (144) is coupled to a self-refresh control circuit (148). The self-refresh control circuit (148) is operable to generate a signal indicating completion of a self-refresh cycle. The refresh row address counter (144) is also coupled to a multiplexer (146). The multiplexer (146) outputs row addresses from either the refresh row address counter (144) or those supplied externally for rows to be refreshed.

Abstract: A process for manufacturing a semiconductor package having two rows of interdigitated leads. The two rows of leads (14, 16) are affixed on and extend from one side of the semiconductor package (10). The two rows of leads (14, 16) are interdigitated with each other in a non-contacting manner. The end portions of the leads (17) are further shaped to form a contact surface for soldering to electrical conductors on a printed circuit board.

Abstract: An oscillator (108) for a standby charge pump (102,104)in a dynamic random access memory part (30) includes a fuse (136). The fuse can be blown after testing the part while selecting redundant memory cells to reduce the frequency of the oscillator and obtain a lower power part. The oscillator (108) also drives the on-chip self-refresh circuits (106) that operate slower in response to the reduced frequency. Selecting redundant circuits also includes eliminating memory cells that pass the pause test, but by only a certain margin. Reducing the frequency of the oscillator driving the self-refresh circuits would otherwise cause failure of the cells that pass the pause test by only the certain margin. The oscillator circuit includes a ring of inverter stages (112) and a fused voltage bias circuit (110) generating one or another set of bias voltages (118,120) to the ring oscillator to alter its frequency of oscillation.

Abstract: Switching circuits controlled by a fuse that can be blown after testing the DRAM part select the timing signals coupled from a binary counter to internal signal generator circuits. The internal Circuits control self refresh in this embodiment. The decision to leave the fuse intact or blow the fuse rests on the test results obtained from each part and can vary depending upon maturity of the manufacturing process, the pause test results obtained and whether a low power part is desired. The fuse is affected after fabrication of the chip and at the same time as other fuses used for redundancy. This provides another degree of freedom in the manufacture of integrated circuits.

Abstract: The present invention provides a modular electronic component (10) wherein a sequence of leads (26) of a lead frame (12) differs from a sequence of bonding pads (16) on an integrated circuit (14). When lead frame (12) is placed adjacent integrated circuit (14), first and second power buses (22) and (24) are disposed on a first side (18) of bonding pads (16). First portion (30) of leads (26) and lead finger (28) are disposed on second side (20) of bonding pads (16). Bonding members (42) couple appropriate bonding pads (16) with corresponding leads (26), first and second power buses (22) and (24), and lead finger (28). In this manner, the pin out of modular electronic component (10) may be altered by incorporating appropriate lead fingers (28) without changing the sequence of bonding pads (16).

Abstract: A memory part (10), with memory (14) subarrays arranged in different ways, provides one data input and output path for normal operation and another data input and output path for test mode operation. The part furnishes one data output multiplexer (40) connected between the memory (14) subarrays and the data output buffers (24) for normal operation. The part furnishes another data output multiplexer (52) connected between the memory (14) subarrays and the data output buffers for test mode operation. Test mode circuits (30) on the memory part select operation of the one and the other multiplexer. Data input gating circuits connect between the data in buffers (22) and the memory (14) subarrays and connect all or one of the data input leads D0-8 to the memory subarrays in response to operation of the test mode circuits.

Abstract: A shorted dual MR head which is magnetically shielded for the purpose of isolating the dual MR head from extraneous magnetic fields and from long wavelength recorded signals which could cause nonlinear distortion of the dual MR head but not shielded for the purpose of improving linear resolution. The magnetic shields do not significantly affect linear resolution of the dual MR head and can be spaced apart from the dual MR head over a wide range of separation distances limited by factors other than the characteristic bit length of the magnetic signal to be resolved. In one embodiment, at least one shielding element for the dual MR head can be one of the poles or other components of an inductive record head and, together, the two heads can form an integrated thin-film inductive record/MR reproduce head assembly.

Abstract: Method and apparatus for reading digital data stored on an optical tape are achieved with a digital optical tape read system including an optical tape and an illumination arrangement. The optical tape has bit cells which are stored along a plurality of tracks of bit cells. Each track includes a line of bit cells, and each bit cell has either a first spot power reflectance representative of a first binary value, or a second spot power reflectance representative of a second binary value. The illumination arrangement functions to illuminate a predetermined area of the optical tape covering a plurality of bit cells with incident light that provides substantially a 180.degree. phase difference between adjacent bit cell locations on the optical tape to be concurrently read.

Abstract: The invention in one embodiment utilizes a pair of identical high energy permanent magnet dipoles mounted on parallel rotatable shafts. The magnetic dipoles lie in a plane perpendicular to the rotatable shafts, and the shafts are coupled to a drive motor for rotation in opposite directions. The magnetic dipoles gives rise to a resultant field which is the sum of the fields due to the individual dipole magnetic moments. With the dipoles aligned, a field having only a longitudinal component is generated, "longitudinal" being defined as being along the direction of initial alignment. The longitudinal components of the two dipoles add, being in the same direction, while the transverse (i.e. perpendicular to the longitudinal direction) components of the dipole cancel, as they point in opposite directions. In the region of space adjacent to the longitudinally defined direction, the longitudinal oriented field components still add, and the transverse components substantially, if not completely, cancel.

Abstract: Fluorescent patterns are provided registratively oriented on a support by coating a liquid precursor of a photolithographically patternable composition, containing fluorescent compounds, on said support and patternwise exposing and developing the coating on the support.

Abstract: Apparatus and a method for generating a multi-level halftone image (104) from a digitally sampled continuous tone image (101). The apparatus includes a control circuit (140), a preference matrix (150) having as its matrix elements addresses of a plurality of look-up tables (160) and a plurality of look-up tables (160) in the form of a look-up table stack (155). Generally, the control circuit (140) instructs the preference matrix (150) to select a look-up table (160) from the look-up table stack (155) in a pre-defined manner. The selected table (160) is used to convert an intensity value (102) into a multi-level pixel value (106) in the halftone image (104). To accomplish the conversion, each look-up table (160) contains a quantized one-dimensional transfer function (165') having as an input the magnitude of the intensity value (102). The magnitude is mapped into an output level by the transfer function as one of a plurality of available levels.

Abstract: In a read/write head for a magneto-optical storage system, a optical wave plate is positioned between the partial polarization beam splitter to which the radiation from the source is applied and the analyzing beam splitter which directs the two components of the radiation beam to the differential detection system. Using the techniques herein described, equations are developed which identify the optimal parameters for the optical wave plate. The equations are derived for the retardation of the optical wave plate and for the angle of the slow axis of the optical wave plate relative to the read/write head optical coordinates. These two equations are given in terms of the phase between the s and the p polarization components. The equations are applied to the specific example wherein TbFeCo is the magneto-optical material.