Patents Represented by Attorney Williams, Morgan & Amerson, P.C.
  • Patent number: 8349740
    Abstract: In sophisticated semiconductor devices, stress-inducing materials may be provided above the basic transistor devices without any etch control or etch stop materials, thereby enabling an efficient de-escalation of the surface topography, in particular above field regions including closely spaced polysilicon lines. Furthermore, an additional stress-inducing material may be provided on the basis of the superior surface topography, thereby providing a highly efficient strain-inducing mechanism in performance-driven transistor elements.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: January 8, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ralf Richter
  • Patent number: 8349694
    Abstract: When forming the strain-inducing semiconductor alloy in one type of transistor of a sophisticated semiconductor device, superior thickness uniformity of a dielectric cap material of the gate electrode structures may be achieved by forming encapsulating spacer elements on each gate electrode structure and providing an additional hard mask material. Consequently, in particular, in sophisticated replacement gate approaches, the dielectric cap material may be efficiently removed in a later manufacturing stage, thereby avoiding any irregularities upon replacing the semiconductor material by an electrode metal.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: January 8, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Markus Lenski, Andy Wei, Martin Gerhardt
  • Patent number: 8352688
    Abstract: A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: January 8, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jaewoong Chung, David S. Christie, Michael P. Hohmuth, Stephan Diestelhorst, Martin T. Pohlack, Luke Yen
  • Patent number: 8352686
    Abstract: An efficient and effective compiler data prefetching technique is disclosed in which memory accesses may be prefetched are represented in linear induction expressions. Furthermore, indirect memory accesses indexed by other memory accesses of linear induction expressions in scalar loops may be prefetched.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: January 8, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Dz-ching Ju
  • Patent number: 8343826
    Abstract: When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage on the basis of a silicon/germanium semiconductor alloy for adjusting appropriate electronic conditions in the channel region, the efficiency of a strain-inducing embedded semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by initiating a crystal growth in the silicon material of the gate electrode structure after the gate patterning process. In this manner, the negative strain of the threshold voltage adjusting silicon/germanium alloy may be reduced or compensated for.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: January 1, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Patent number: 8344474
    Abstract: In a sophisticated metallization system, self-aligned air gaps may be provided in a locally selective manner by using a radiation sensitive material for filling recesses or for forming therein the metal regions. Consequently, upon selectively exposing the radiation sensitive material, a selective removal of exposed or non-exposed portions may be accomplished, thereby resulting in a highly efficient overall manufacturing flow.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: January 1, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert Seidel, Thomas Werner
  • Patent number: 8338892
    Abstract: In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residues at the top area of the gate electrode structure, a certain degree of corner rounding of the semiconductor material may be introduced, which may be accomplished by ion implantation prior to epitaxially growing the strain-inducing semiconductor material. This concept may be advantageously combined with the provision of sophisticated high-k metal gate electrodes that are provided in an early manufacturing stage.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: December 25, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Roman Boschke, Maciej Wiatr, Peter Javorka
  • Patent number: 8338274
    Abstract: In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of a strain-inducing semiconductor alloy. To this end, strain relaxation implantation processes may be performed at the drain side according to some illustrative embodiments, while, in other cases, the deposition of the strain-inducing alloy may be performed in an asymmetric manner with respect to the drain side and the source side of the transistor.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: December 25, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Vassilios Papageorgiou, Gunda Beernink, Jan Hoentschel
  • Patent number: 8338314
    Abstract: In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ralf Richter, Heike Salz, Robert Seidel
  • Patent number: 8338306
    Abstract: In a replacement gate approach, the polysilicon material may be efficiently removed during a wet chemical etch process, while the semiconductor material in the resistive structures may be substantially preserved. For this purpose, a species such as xenon may be incorporated into the semiconductor material of the resistive structure, thereby imparting a significantly increased etch resistivity to the semiconductor material. The xenon may be incorporated at any appropriate manufacturing stage.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: December 25, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jens Heinrich, Ralf Richter, Katja Steffen, Johannes Groschopf, Frank Seliger, Andreas Ott, Manfred Heinz, Andy Wei
  • Patent number: 8339166
    Abstract: An integrated circuit device includes first circuitry including first logic devices and a clock tree for distributing a clock signal to the first logic devices and second circuitry including second logic devices and a clock gater operable to receive the clock signal and distribute the clock signal to the second logic devices. The clock gater comprises a programmable delay circuit.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Deepesh John, Sundararajan Rangarajan
  • Patent number: 8338284
    Abstract: In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: December 25, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kai Frohberg, Hartmut Ruelke, Volker Jaschke, Joerg Hohage, Frank Seliger
  • Patent number: 8334573
    Abstract: Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer prior to a sequence for patterning active regions and forming a strain-inducing semiconductor alloy therein, wherein, in particular, the corresponding cleaning process prior to the selective epitaxial growth process has been identified as a major source for causing deposition-related irregularities upon depositing the interlayer dielectric material.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: December 18, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Maciej Wiatr, Markus Forsberg, Stephan Kronholz, Roman Boschke
  • Patent number: 8332783
    Abstract: Variations in critical dimensions of circuit features of sophisticated semiconductor devices may be reduced by efficiently extracting mask and/or imaging tool specific non-uniformities with high spatial resolution by using measured intensity values and simulated intensity values. For example, a tool internal radiation sensor may be used for measuring the intensity of an image of a lithography mask, while a simulated intensity enables eliminating the mask pattern specific intensity contributions. In this manner, high spatial resolution of the corresponding correction map may be obtained without undue effort in terms of man power and measurement tool resources.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: December 11, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rolf Seltmann, Stefan Roling, Francois Weisbuch
  • Patent number: 8329577
    Abstract: By introducing a metallic species into an exposed surface area of a copper region, the electromigration behavior of this surface area may be significantly enhanced. The incorporation of the metallic species may be accomplished in a highly selective manner so as to not unduly affect dielectric material positioned adjacent to the metal region, thereby essentially avoiding undue increase of leakage currents.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: December 11, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Matthias Lehr, Moritz-Andreas Meyer, Eckhard Langer
  • Patent number: 8329531
    Abstract: In sophisticated semiconductor devices, the initial strain component of a globally strained semiconductor layer may be substantially preserved during the formation of shallow trench isolations by using a rigid mask material, which may efficiently avoid or reduce a deformation of the semiconductor islands upon patterning the isolation trenches. Consequently, selected regions with high internal stress levels may be provided, irrespective of the height-to-length aspect ratio, which may limit the application of globally strained semiconductor layers in conventional approaches. Furthermore, in some illustrative embodiments, active regions of substantially relaxed strain state or of inverse strain type may be provided in addition to the highly strained active regions, thereby enabling an efficient process strategy for forming complementary transistors.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: December 11, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Sven Beyer, Uwe Griebenow, Thilo Scheiper
  • Patent number: 8329526
    Abstract: Dielectric cap layers of sophisticated high-k metal gate electrode structures may be efficiently removed on the basis of a sacrificial fill material, thereby reliably preserving integrity of a protective sidewall spacer structure, which in turn may result in superior uniformity of the threshold voltage of the transistors. The sacrificial fill material may be provided in the form of an organic material that may be reduced in thickness on the basis of a wet developing process, thereby enabling a high degree of process controllability.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: December 11, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jens Heinrich, Frank Seliger, Ralf Richter, Markus Lenski
  • Patent number: 8330534
    Abstract: An integrated circuit device includes a first circuit for providing current to a first node, and a degradation compensator including a first compensation circuit coupled to the first node to provide compensation current to the first node. The degradation compensator is operable to estimate a degree of degradation in the first circuit and provide a compensation signal to the first compensation circuit to control the amount of compensation current based on the estimated degree of degradation.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: December 11, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bo Zhai, Wesley Favors, Singh Teja
  • Patent number: 8322427
    Abstract: A method of reducing a pressure within a first cavity of a subsea device is disclosed which includes transferring fluid within the first cavity to an accumulator, increasing a pressure of the fluid within the accumulator and, after increasing the pressure of the fluid within the accumulator, transferring at least some of the fluid in the accumulator into a second cavity, wherein the second cavity is at a higher pressure than said first cavity.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: December 4, 2012
    Assignee: FMC Kongsberg Subsea AS
    Inventors: Olav Inderberg, John A. Johansen
  • Patent number: 8324091
    Abstract: During a manufacturing sequence for forming a sophisticated high-k metal gate structure, a cover layer, such as a silicon layer, may be deposited on a metal cap layer in an in situ process in order to enhance integrity of the metal cap layer. The cover layer may provide superior integrity during the further processing, for instance in view of performing wet chemical cleaning processes and the subsequent deposition of a silicon gate material.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: December 4, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Joachim Metzger, Robert Binder, Markus Lenski, Klaus Hempel