Abstract: By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.

Abstract: A communication system includes a bus, first and second devices coupled to the bus, and a handshaking unit. The bus includes at least one data line and control lines. The data line is coupled between the first and second devices. The handshaking unit is coupled to the control lines of the bus and is adapted to determine if the first and second devices are capable of completing a data transfer and enable the first and second devices to facilitate the data transfer. A method for interfacing first and second devices coupled to a bus is provided. The bus has at least one data line coupled to the first and second devices and control lines. The method includes determining if the first and second devices are capable of completing a data transfer based on the control lines; providing handshaking signals on the control lines to enable the first and second devices; and transferring the data over the data line in response to the handshaking signals.

Abstract: By providing a gate dielectric material of increased thickness for P-channel transistors compared to N-channel transistors, degradation mechanisms, such as negative bias threshold voltage instability, hot carrier injection and the like, may be reduced. Due to the enhanced reliability of the P-channel transistors, overall production yield for a specified quality category may be increased, due to the possibility of selecting narrower guard bands for the semiconductor device under consideration.

Abstract: A method and apparatus for providing an override of an operational mode of an implantable medical device. An override input to enter an override mode is received. A determination as to whether a magnetic input has been received is made. A predetermined response to the magnetic input is blocked in response to receiving the override input.

Abstract: By forming two or more individual dielectric layers of high intrinsic stress levels with intermediate interlayer dielectric material, the limitations of respective deposition techniques, such as plasma enhanced chemical vapor deposition, may be respected while nevertheless providing an increased amount of stressed material above a transistor element, even for highly scaled semiconductor devices.

Abstract: A measurement device is disclosed which includes a structure adapted to be removably coupled to a Christmas tree, a sleeve operatively coupled to the structure and a flowmeter positioned at least partially within the sleeve.

Abstract: By forming a conductive material within an etch mask for an anisotropic etch process for patterning openings, such as vias, in a dielectric layer of a metallization structure, the probability for arcing events may be reduced, since excess charge may be laterally distributed. For example, an additional sacrificial conductive layer may be formed or an anti-reflecting coating (ARC) may be provided in the form of a conductive material in order to obtain the lateral charge distribution.

Abstract: A method for production planning includes receiving a first order quantity of a first device. A first yield estimate of the first device from a production line is determined. The first yield estimate is adjusted based on a first confidence factor associated with the first order quantity. A dispatch quantity for processing in the production line is determined based on the first order quantity and the adjusted first yield estimate.

Abstract: By providing two or more consumable electrodes within a single reactor vessel, an alloy having a high degree of chemical ordering may be deposited in situ in that the current flows of the individual consumable electrodes are controlled to obtain a substantially layered deposition of the two or more metals. Hence, especially in copper-based metallization layers, the advantage of enhanced resistance against electromigration offered by alloys may be achieved without unduly reducing the overall conductivity.

Abstract: Generally, the present disclosure is directed to a method of removing “weakened” areas of a metal silicide layer during silicide layer formation, thereby reducing the likelihood that material defects might occur during subsequent device manufacturing. One illustrative embodiment includes depositing a first layer of a refractory metal on a surface of a silicon-containing material, and performing first and second heating processes. The method further comprises performing a cleaning process, depositing a second layer of the refractory metal above the silicon-containing material, and performing a third heating process.

Abstract: By suppressing the presence of free oxygen during a cleaning process and a subsequent electrochemical deposition of a seed layer, the quality of a corresponding interface between the barrier material and the seed layer may be enhanced, thereby also improving performance and the characteristics of the finally obtained metal region. Thus, by identifying free oxygen as a main source for negatively affecting the characteristics of metals during a “direct on barrier” plating process, efficient strategies have been developed and are disclosed herein to provide a reliable technique for volume production of sophisticated semiconductor devices.

Abstract: A system and a method of operating a chemical mechanical polishing (CMP) system comprises a slurry delivering unit configured for locally varying the supply of slurry while polishing the substrate. To this end, the slurry delivering unit may comprise at least one slurry outlet over a polishing pad of the CMP system, wherein the at least one slurry outlet is controllably movable to distribute slurry over the polishing pad.

Abstract: By dividing a single chip area into individual sub-areas, a thermally induced stress in each of the sub-areas may be reduced during operation of complex integrated circuits, thereby enhancing the overall reliability of complex metallization systems comprising low-k dielectric materials or ULK material. Consequently, a high number of stacked metallization layers in combination with increased lateral dimensions of the semiconductor chip may be used compared to conventional strategies.

Abstract: A screen for a vibratory separator, the screen including at least two layers of screening material, including a first layer and a second layer, the first layer made of a plurality of intersecting first wires, the second layer made of a plurality of intersecting second wires, the first wires including first shute wires and first warp wires, the second wires including second shute wires and second warp wires, certain of the first warp wires aligned with a second warp wire, and/or certain of the first shute wires aligned with a second shute wire. This abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure and is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims, 37 CFR 1.72(b).

Abstract: A method includes determining at least a first characteristic of a device during a first test insertion and storing the first characteristic. The device is identified during a second test insertion. The first characteristic is retrieved responsive to the identification of the device. A test program for the second insertion is configured based on the first characteristic. The configured test program is executed to test the device during the second test insertion.

Abstract: A method includes determining production targets for devices of different types in a production line. A queue level of devices of a first type that have completed performance of a first operation configured in accordance with a first setup state in the production line and await performance of a second operation in the production line is determined. Based on the determined queue level, a second type of device is selected for subsequent processing in the first operation based on the production targets and a setup time associated with configuring the first operation from the first setup state to a second setup state associated with the second type of device. The first operation is configured in accordance with the second setup state for processing devices of the second type.

Abstract: When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap layers of transistors may have experienced a different process history and may thus require a subsequent adaptation of the final cap layer thickness in one type of the transistors. For this purpose, a hard mask material may be used during a process sequence for forming offset spacer elements in one gate electrode structure while covering another gate electrode structure.

Abstract: When forming a complex metallization system in which vias of different lateral size have to be provided, a split patterning sequence may be applied. For this purpose, a lithography process may be specifically designed for the critical via openings and a subsequent second patterning process may be applied for forming the vias of increased lateral dimensions, while the critical vias are masked. In this manner, superior process conditions may be established for each of the patterning sequences.

Abstract: In extremely scaled semiconductor devices, an asymmetric transistor configuration may be established on the basis of tilted implantation processes with increased resist height and/or tilt angles during tilted implantation processes by providing an asymmetric mask arrangement for masked transistor elements. For this purpose, the implantation mask may be shifted by an appropriate amount so as to enhance the overall blocking effect for the masked transistors while reducing any shadowing effect of the implantation masks for the non-masked transistors. The shift of the implantation masks may be accomplished by performing the automatic alignment procedure on the basis of “shifted” target values or by providing asymmetrically arranged photolithography masks.

Abstract: A method, apparatus, and a system for performing a product feedback for process control are provided. Metrology data relating to a first workpiece is received. An end of line parameter relating to the first workpiece is received. The end of line parameter is correlated with the metrology data. A process control associated with a plurality of processes to be performed on a second workpiece is adjusted based upon the correlating.