Patents Represented by Attorney Williams, Morgan & Amerson, P.C.

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  • Method and apparatus for extracting data from a data store
    Patent number: 8051093
    Abstract: A method includes defining a general query for extracting data from at least one data store operable to store workpiece data associated with the processing of workpieces in a manufacturing system. The general query specifies at least one ambiguous parameter having a plurality of potential values. Metadata associated with the workpiece data is accessed. The metadata is employed to identify a plurality of candidate values for the at least one ambiguous parameter. A plurality of atomic queries is generated. Each atomic query is associated with one of the candidate values. The plurality of atomic queries is executed to extract data from the at least one data store and generate an output report including the extracted data.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: November 1, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: George M. Kaupas, Sundeep Kunchala, Andrew P. Haskins
  • Wire bonding on reactive metal surfaces of a metallization of a semiconductor device by providing a protective layer
    Patent number: 8043956
    Abstract: In semiconductor devices having a copper-based metallization system, bond pads for wire bonding may be formed directly on copper surfaces, which may be covered by an appropriately designed protection layer to avoid unpredictable copper corrosion during the wire bond process. A thickness of the protection layer may be selected such that bonding through the layer may be accomplished, while also ensuring a desired high degree of integrity of the copper surface.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: October 25, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Matthias Lehr, Frank Kuechenmeister
  • Method of reducing non-uniformities during chemical mechanical polishing of excess metal in a metallization level of microstructure devices
    Patent number: 8039398
    Abstract: Prior to performing a CMP process for planarizing a metallization level of an advanced semiconductor device, an appropriate cap layer may be formed in order to delay the exposure of metal areas of reduced height level to the highly chemically reactive slurry material. Consequently, metal of increased height level may be polished with a high removal rate due to the mechanical and the chemical action of the slurry material, while the chemical interaction with the slurry material may be substantially avoided in areas of reduced height level. Therefore, a high process uniformity may be achieved even for pronounced initial surface topographies and slurry materials having a component of high chemical reactivity.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Frank Feustel, Robert Seidel, Juergen Boemmels
  • Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility
    Patent number: 8039878
    Abstract: By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel may be oriented along the <100> direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: October 18, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Igor Peidous, Thorsten Kammler, Andy Wei
  • Enhanced integrity of a high-K metal gate electrode structure by using a sacrificial spacer for cap removal
    Patent number: 8039342
    Abstract: In a process strategy for forming sophisticated high-k metal gate electrode structures in an early manufacturing phase, the dielectric cap material may be removed on the basis of a protective spacer element, thereby ensuring integrity of a silicon nitride sidewall spacer structure, which may preserve integrity of sensitive gate materials and may also determine the lateral offset of a strain-inducing semiconductor material.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: October 18, 2011
    Assignee: GlobalFoundries Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Andy Wei
  • Method and test structure for estimating focus settings in a lithography process based on CD measurements
    Patent number: 8040497
    Abstract: By encoding process-related non-uniformities, such as different height levels, which may be caused by CMP or other processes during the fabrication of complex device levels, such as metallization structures, respective focus parameter settings may be efficiently evaluated on the basis of well-established CD measurement techniques.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas Werner, Frank Feustel, Kai Frohberg
  • Method for secure authentication of mobile devices
    Patent number: 8041339
    Abstract: A method for authenticating a mobile device is provided. The method includes receiving a communication request from the mobile device. The mobile device is operable to exchange data over a primary channel. Authentication data is received from the mobile device over a second channel. The secondary channel is a short-range channel operable for exchanging data when the mobile device is within physical proximity. The authentication data is processed to determine whether the mobile device is a trusted device.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: October 18, 2011
    Assignee: Alcatel Lucent
    Inventors: Harold Wilhelm Antonie Teunissen, Jacco Brok, Ko Marcus Joannes Louis Lagerberg, Miroslav Zivkovic
  • Method for reducing defects of gate of CMOS devices during cleaning processes by modifying a parasitic PN junction
    Patent number: 8039338
    Abstract: By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Manfred Horstmann, Peter Javorka, Karsten Wieczorek, Kerstin Ruttloff
  • Determining die test protocols based on process health
    Patent number: 8041518
    Abstract: A method includes receiving a first set of parameters associated with a subset of a plurality of die on a wafer. A die health metric is determined for at least a portion of the plurality of die based on the first set of parameters. The die health metric includes at least one process component associated with the fabrication of the die and at least one performance component associated with an electrical performance characteristic of the die. At least one of the die is tested. A protocol of the testing is determined based on the associated die health metric.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Michael G. McIntyre, Kevin R. Lensing
  • Method and apparatus for identifying broken pins in a test socket
    Patent number: 8040140
    Abstract: A method includes scanning a test socket after removal of a device under test to generate scan data. The scan data is compared to reference data. A presence of at least a portion of a pin in the test socket is identified based on the comparison. A test system includes a test socket, a scanner, and a control unit. The test socket is operable to receive devices under test. The scanner is operable to scan a test socket after removal of a device under test to generate scan data. The control unit is operable to compare the scan data to reference data and identify a presence of at least a portion of a pin in the test socket based on the comparison.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Matthew S. Ryskoski, Christopher L. Wooten, Song Han, Douglas C. Kimbrough
  • Reducing contamination of semiconductor substrates during BEOL processing by performing a deposition/etch cycle during barrier deposition
    Patent number: 8039400
    Abstract: A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Frank Koschinsky, Matthias Lehr, Holger Schuehrer
  • Intelligent document scanning
    Patent number: 8041126
    Abstract: A method, apparatus, and system, for scanning a first portion of a data to generate a second portion of data is provided. A control parameter relating to a level of detail associated with filtering a first portion of data is received. The filtering of the first portion of data is performed based upon the control parameter. The filtering of the first portion of data includes a rule-based filtering, a context-based filtering, a statistical-based filtering, or a semantic-based filtering. Performing the filtering provides for a reduction of a portion of the first portion of data. A second portion of data that is smaller than the first portion of data is provided based upon the filtering of the first portion of data.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: October 18, 2011
    Assignee: Apple Inc.
    Inventors: Devang K. Naik, Kim E. A. Silverman
  • Technique for forming embedded metal lines having increased resistance against stress-induced material transport
    Patent number: 8039395
    Abstract: An alloy forming dopant material is deposited prior to the formation of a copper line, for instance by incorporating the dopant material into the barrier layer, which is then driven into the vicinity of a weak interface by means of a heat treatment. As indicated by corresponding investigations, the dopant material is substantially transported to the weak interface through grain boundary regions rather than through the bulk copper material (copper grains), thereby enabling moderately high alloy concentrations in the vicinity of the interface while maintaining a relatively low overall concentration within the grains. The alloy at the interface reduces electromigration along the interface.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: October 18, 2011
    Assignee: Globalfoundries Inc.
    Inventors: Moritz-Andreas Meyer, Hans-Juergen Engelmann, Ehrenfried Zschech, Peter Huebler
  • Drive current adjustment for transistors formed in the same active region by locally providing embedded strain-inducing semiconductor material in the active region
    Patent number: 8034669
    Abstract: The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of different strain levels obtained by providing at least one embedded semiconductor alloy in the active region, thereby providing a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices, in which a pronounced variation of the transistor width is conventionally used to adjust the ratio of the drive currents for the pull-down and pass transistors.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: October 11, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel
  • Transistor with asymmetric silicon germanium source region
    Patent number: 8035098
    Abstract: The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: October 11, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jian Chen, James F. Buller, Akif Sultan
  • Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materials
    Patent number: 8034726
    Abstract: By forming a buffer material above differently stressed contact etch stop layers followed by the deposition of a further stress-inducing material, enhanced overall device performance may be accomplished, wherein an undesired influence of the additional stress-inducing layer may be reduced in device regions, for instance, by removing the additional material or by performing a relaxation implantation process. Furthermore, process uniformity during a patterning sequence for forming contact openings may be enhanced by partially removing the additional stress-inducing layer at an area at which a contact opening is to be formed.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: October 11, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ralf Richter, Michael Finken, Joerg Hohage, Heike Salz
  • Connection manager with location learning
    Patent number: 8032150
    Abstract: A method for configuring a mobile device including a plurality of communication interfaces is provided. A first network configuration identifying communication networks accessible through the communication interfaces of the mobile device is identified. The first network configuration is compared to a plurality of previously encountered network configurations. A location of the mobile device associated with the first network configuration is designated responsive to the first network configuration being included in the plurality of previously encountered network configurations. Usage patterns of the communication interfaces at the designated location are tracked. Connectivity is established for the mobile device to a remote network through the communication interfaces based on the usage patterns.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: October 4, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Terry L. Cole
  • Structured strained substrate for forming strained transistors with reduced thickness of active layer
    Patent number: 8030148
    Abstract: In a strained SOI semiconductor layer, the stress relaxation which may typically occur during the patterning of trench isolation structures may be reduced by selecting an appropriate reduced target height of the active regions, thereby enabling the formation of transistor elements on the active region of reduced height, which may still include a significant amount of the initial strain component. The active regions of reduced height may be advantageously used for forming fully depleted field effect transistors.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: October 4, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jan Hoentschel, Andy Wei, Sven Beyer
  • Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer
    Patent number: 8030209
    Abstract: During the formation of metallization layers of sophisticated semiconductor devices, the damaging of sensitive dielectric materials, such as ULK materials, may be significantly reduced during a CMP process by applying a compressive stress level. This may be accomplished, in some illustrative embodiments, by forming a compressively stressed cap layer on the ULK material, thereby suppressing the propagation of micro cracks into the ULK material.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: October 4, 2011
    Assignee: GLOBALFOUNDDRIES Inc.
    Inventors: Thomas Werner, Kai Frohberg, Frank Feustel
  • Recessed drain and source areas in combination with advanced silicide formation in transistors
    Patent number: 8026134
    Abstract: During the manufacturing process for forming sophisticated transistor elements, the gate height may be reduced and a recessed drain and source configuration may be obtained in a common etch sequence prior to forming respective metal silicide regions. Since the corresponding sidewall spacer structure may be maintained during the etch sequence, controllability and uniformity of the silicidation process in the gate electrode may be enhanced, thereby obtaining a reduced degree of threshold variability. Furthermore, the recessed drain and source configuration may provide reduced overall series resistance and enhanced stress transfer efficiency.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: September 27, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Griebenow, Andy Wei, Jan Hoentschel, Thilo Scheiper