Abstract: A seek-scan-probe memory device, utilizing a media electrode to allow active cantilevers to contact the storage media, and a pull electrode to pull up cantilevers away from the storage media when in an inactive mode. Other embodiments are described and claimed.

Abstract: A non-volatile microelectronic memory that has a memory cell array, which includes memory cell string pairs that share a bitline contact, that have separate source lines, and that have at least two transistors within each memory cell string that may be programming for sharing the bitline contact.

Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.

Abstract: A method of forming a microball grid array includes adhering a microball precursor material to a transfer medium under conditions to reflect a selective charge pattern. The method includes transferring the microball precursor material from the transfer medium across a gap and to an integrated circuit substrate under conditions to reflect the selective charge pattern. The method includes achieving the microball grid array without the aid of a mask.

Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract: A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.

Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.

Abstract: Methods of fabricating an array capacitor are disclosed, in which via structures of the array capacitor have increased uniformity in their transverse areas. One method involves perforating a capacitor body to form first holes extending from a first surface and partially through the capacitor body. The capacitor body may be further perforated to form second holes extending from a second opposed surface of the capacitor body. The second holes are to connect to the first holes to provide through holes extending across a thickness of the capacitor body. An appropriate conductive material may then be filled in the through holes to form via structures with increased uniformity in their transverse areas.

Abstract: A composition includes a bismaleimide triazine (BT) compound with a nanoclay composited therewith. A mounting substrate includes polymer compound with a nanoclay composited therewith to form a core for the mounting substrate. A process includes melt blending a polymer such as BT with a nanoclay and forming a core. A process includes dissolving a monomer such as BT with a nanoclay and forming a core. A system includes a nanoclay dispersed in a polymer matrix and a microelectronic device mounted on the mounting substrate that includes the nanoclay dispersed in the polymer matrix.

Abstract: Techniques are provided for efficient wafer layout, which include the use of an offset grid to optimize use of available wafer space. As such, the number of identical die that can be fabricated on the wafer can be increased, relative to a standard perpendicular grid. By adding additional registration marks, an increase in flexibility of where each row/column of fields can be printed is enabled. This increased level of freedom in-turn allows for the optimization of the number of die that each row/column can contain, and translates directly into an increase in the number of yielding die per wafer. In addition, techniques are provided that allow for the dicing of individual die in a non-Cartesian coordinated manner. However, conventional singulation techniques can be used as well, given attention to the offset grid lines.

Abstract: An integrated heat spreader is disclosed in which grooves are formed in a recess of the heat spreader to enhance the stiffness and strength of the integrated heat spreader without increasing production costs or complexity. The integrated heat spreader may be fabricated by providing a metal strip having raised portions thereon to provide a recess therebetween, forming grooves on a bottom surface of the recess, where the grooves extend along a periphery of the bottom surface which is substantially free of the raised portions, and subsequently singulating an integrated heat spreader from the metal strip.

Abstract: A method of grinding a molded semiconductor package to a desired ultra thin thickness without damage to the package is disclosed. Prior to grinding a molded package to a desired package thickness, the package may be protected from excessive mechanical stress generated during grinding by applying a protective tape to enclose interconnects formed on the package. This way, the protective tape provides support to the semiconductor package during package grinding involving the mold material as well as the die. In the post-grind package, the grinded die surface may be exposed and substantially flush with the mold material. The protective tape may then be removed to prepare the post-grind package for connection with an external device or PCB.

Abstract: A microelectronic package having a radio frequency (RF) amplifier circuit and, incorporating harmonic rejection filters and matching circuits integrally formed in the package is disclosed. A harmonic rejection filter may comprise a metal-insulator-metal (MIM) capacitor serially coupled between bond pads disposed on a RF amplifier circuit die, a first wire bond coupling a first bond pad to a package output, where the first bond pad is coupled to the output of the RF amplifier, and a second wire bond coupling a second bond pad to a package ground. The harmonic rejection filter may be appropriately configured to filter one or more harmonics at different frequencies.

Abstract: A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.

Abstract: Embodiments of the present invention describe a method of fabricating low resistance contact layers on a semiconductor device. The semiconductor device comprises a substrate having source and drain regions. The substrate is alternatingly exposed to a first precursor and a second precursor to selectively deposit an amorphous semiconductor layer onto each of the source and drain regions. A metal layer is then deposited over the amorphous semiconductor layer on each of the source and drain regions. An annealing process is then performed on the substrate to allow the metal layer to react with amorphous semiconductor layer to form a low resistance contact layer on each of the source and drain regions. The low resistance contact layer on each of the source and drain regions can be formed as either a silicide layer or germanide layer depending on the type of precursors used.

Abstract: Embodiments of the present invention describe a removal chemistry for removing hard mask. The removal chemistry is a wet-etch solution that removes a metal hard mask formed on a dielectric layer, and is highly selective to a metal conductor layer underneath the dielectric layer. The removal chemistry comprises an aqueous solution of hydrogen peroxide (H2O2), a hydroxide source, and a corrosion inhibitor. The hydrogen peroxide and hydroxide source have the capability to remove the hard mask while the corrosion inhibitor prevents the metal conductor layer from chemically reacting with the hydrogen peroxide and hydroxide source during the hard mask removal.

Abstract: Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.

Abstract: The present invention describes an aperture including: an opaque plate; two sliver openings located in the opaque plate, the two sliver openings having rectangular shapes, the two sliver openings being parallel to each other. The present invention further describes a method including: decomposing a pattern into horizontal sub-features and vertical sub-features; forming a first mask corresponding to the horizontal sub-features; forming a second mask corresponding to the vertical sub-features; forming a first aperture with two parallel horizontal sliver openings corresponding to the first mask; forming a second aperture with two parallel vertical sliver openings corresponding to the second mask; exposing a wafer using the first aperture and the first mask; exposing the wafer using the second aperture and the second mask; and exposing the wafer with the third mask.

Abstract: The present disclosure relates to fabricating substrates for use in microelectronic device packages. In at least one embodiment, two substrate cores may be attached together during build-up layer formation on each substrate core to increase substrate fabrication throughput. The embodiments of the present disclosure may allow the processing of relatively thin substrates.