Abstract: Embodiments of the invention relate to a method of fabricating logic transistors using replacement metal gate (RMG) logic flow with modified process to form recessed channel array transistors (RCAT) on a common semiconductor substrate. An embodiment comprises forming an interlayer dielectric (ILD) layer on a semiconductor substrate, forming a first recess in the ILD layer of a first substrate region, forming a recessed channel in the ILD layer and in the substrate of a second substrate region, depositing a first conformal high-k dielectric layer in the first recess and a second conformal high-k dielectric layer in the recessed channel, and filling the first recess with a first gate metal and the recessed channel with a second gate metal.

Abstract: A transistor structure and a method of forming same. The transistor structure includes: a semiconductor substrate having a gate-side surface; a gate disposed on the gate-side surface, the gate extending above the gate-side surface by a first height; a semiconductor extension disposed on the gate-side surface and extending above the gate-side surface by a second height larger than the first height, the semiconductor extension including a diffusion region having a diffusion surface located at the second height; and a diffusion contact element electrically coupled to the diffusion surface.

Abstract: A method of forming a microelectronic package is provided. The method includes providing a silicon substrate having a plurality of carbon nanotubes disposed on a silicon layer and coupling the silicon substrate to a top surface of a packaging substrate, wherein the plurality of carbon nanotubes are coupled to a plurality of substrate pads of the packaging substrate. The method also includes removing the silicon substrate from the packaging substrate and disposing a die adjacent to the top surface of the packaging substrate, wherein the plurality of carbon nanotubes are coupled to a plurality of bump pads of the die.

Abstract: A seek-scan-probe memory device, utilizing a media electrode to allow active cantilevers to contact the storage media, and a pull electrode to pull up cantilevers away from the storage media when in an inactive mode. Other embodiments are described and claimed.

Abstract: Methods for removing random or uncontrolled surface defects from a work piece surface are provided, by applying a plurality of induced controlled defects over the random defects to alter the surface texture.

Abstract: A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate.

Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

Abstract: The present invention describes an aperture including: an opaque plate; two sliver openings located in the opaque plate, the two sliver openings having rectangular shapes, the two sliver openings being parallel to each other. The present invention further describes a method including: decomposing a pattern into horizontal sub-features and vertical sub-features; forming a first mask corresponding to the horizontal sub-features; forming a second mask corresponding to the vertical sub-features; forming a first aperture with two parallel horizontal sliver openings corresponding to the first mask; forming a second aperture with two parallel vertical sliver openings corresponding to the second mask; exposing a wafer using the first aperture and the first mask; exposing the wafer using the second aperture and the second mask; and exposing the wafer with the third mask.

Abstract: Embodiments of the present invention describe a method of forming nickel sulfide layer on a semiconductor device. A nickel sulfide layer is formed on a substrate by alternatingly exposing the substrate to a nickel-containing precursor and a sulfur-containing precursor.

Abstract: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor.

Abstract: A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks, to share a test access mechanism. During test mode, the test architecture is configured to decouple clock sources of the test access mechanism, the scan controllers and the scan chains.

Abstract: A pellicle is attached to a reticle by a soft adhesive. The distortion of the reticle is less than if a hard adhesive were used.

Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a first body with a plurality of composite bumps thereon, the composite bumps comprising a solder and magnetic particles. The method also includes applying a magnetic field to the magnetic particles to generate sufficient heat to melt the solder and form molten bump regions containing the magnetic particles therein. The method also includes coupling a second body to the first body through the molten bump regions, and cooling the molten bump regions to form solidified composite bumps coupling the second body to the first body. Other embodiments are described and claimed.

Abstract: An annealing method and apparatus for semiconductor manufacturing is described. The method and apparatus allows an anneal that can span a thermal budget and be tailored to a specific process and its corresponding activation energy. In some cases, the annealing method spans a timeframe from about 1 millisecond to about 1 second. An example for this annealing method includes a sub-second anneal method where a reduction in the formation of nickel pipes is achieved during salicide processing. In some cases, the method and apparatus combine the rapid heating rate of a sub-second anneal with a thermally conductive substrate to provide quick cooling for a silicon wafer. Thus, the thermal budget of the sub-second anneal methods may span the range from conventional RTP anneals to flash annealing processes (including duration of the anneal, as well as peak temperature). Other embodiments are described.

Abstract: A group III-V material device has multiple spacer regions above a quantum well channel region. A high-k value gate dielectric is formed on an InGaAs spacer above the quantum well channel region while there are InAlAs spacer regions under contact regions.

Abstract: The present invention discloses a mask including: a first region near a corner of a feature, the first region including a first element, the first element being transparent to a light, the first element having a side that is smaller than a wavelength of said light; a second region near the corner of the feature, the second region including a second element, the second element being transparent to the light, the second element having a side that is smaller than the wavelength of the light; and a third region near the corner of the feature, the third region including a third element, the third element being opaque to the light, the third element having a side that is smaller than the wavelength of the light.

Abstract: Embodiments employ a method to define points on selected nets in a netlist for a focused ion beam (FIB) to create open circuits. A selected net is partitioned into a set of sub-segments, and after considering all metal layers at and above that of the selected net, a subset of the set of sub-segments is formed as those sub-segments having minimum distances from the considered metal layers greater than some threshold. All contiguous sub-segments in the subset of the set of sub-segments are grouped into groups. The midpoints of such groups, and any isolated sub-segments, are possible candidate for FIB points. For some embodiments, the midpoint of the longest (or one of the longest) groups of sub-segments is chosen as the FIB point for the selected net. Other embodiments are described and claimed.

Abstract: The present invention describes a method of and an apparatus for providing a wafer, the wafer including Silicon; etching trenches in the wafer to form Silicon fins; filling Silicon Oxide in the trenches; planarizing the Silicon Oxide; recessing the Silicon Oxide to a first thickness to form exposed Silicon pedestals from the Silicon fins; depositing SiGe over the exposed Silicon pedestal; recessing the Silicon Oxide to a second thickness; undercutting the exposed Silicon pedestals to form necked-in Silicon pedestals; oxidizing thermally and annealing the SiGe; and forming Germanium nanowires.

Abstract: A device is annealed in a deuterium atmosphere. Deuterium penetrates the device to a boundary, which is passivated by the deuterium.

Abstract: A method of forming a notched-base spacer profile for non-planar transistors includes providing a semiconductor fin having a channel region on a substrate and forming a gate electrode adjacent to sidewalls of the channel region and on a top surface of the channel region, the gate electrode having on a top surface a hard mask. a spacer layer is deposited over the gate and the fin using a enhanced chemical vapor deposition (PE-CVD) process. A multi-etch process is applied to the spacer layer to form a pair of notches on laterally opposite sides of the gate electrode, wherein each notch is located adjacent to sidewalls of the fin and on the top surface of the fin.