Abstract: A graphical user interface is implemented with unique icons for registered but not mounted file systems, registered and mounted file systems, and mounted but not registered file systems. The unique icon for the registered but not mounted file systems permits management of such file systems by users within the network.

Abstract: A graphics controller which performs display list-based video refresh operations that enable objects with independent frame rates to be efficiently assembled is disclosed. The graphics controller maintains a virtual display refresh list (VDRL) comprising a plurality of pointers to scan line segments in memory. The graphics controller also creates, maintains, and deletes draw display lists (DDLs) that comprise pointers to object display list subroutines (ODLs) that independently draw objects in memory. The ODLs may allocated one or more buffers in memory into which different frames of the objects are drawn. When an ODL has completed executing, the corresponding pointer in the DDL may be updated to point to the buffer location in memory that stores the newly completed object frame. The VDRL is maintained independently (and may be doubled-buffered) and is updated using the DDLs.

Abstract: A method for performing trench isolation during semiconductor device fabrication is disclosed. The method includes patterning a hard mask to define active areas and isolations areas on a substrate, and forming spacers along edges of the hard mask. Trenches are then formed in the substrate using the spacers as a mask, thereby increasing the width of the substrate under the active areas and increasing Weff for the device.

Abstract: A apparatus and method for cross-referencing routines in software is implemented. Declarations in the software program are searched for routine declarations. For each routine declaration found, an entry in a first table in a database is generated and a routine identifier for the routine entered. In response to each identifier entered, the routines corresponding thereto are searched for calls to other routines. For each call, entry in a second table is generated in which, in a first field, the identifier of the routine being searched is written, and in a second field, an identifier for the called routine is written. The user may select for outputting the routines called by a particular routine, in which case, the entries are accessed via the first field and the contents of the second field are output. Alternatively, the user may select for outputting the routines called by a particular routine, in which case the entries are accessed via the second field and the contents of the first field are output.

Abstract: Lighting parameters are received as floating-point numbers from a software application via an application programming interface (API). The floating-point numbers are converted to a fixed-point representation having a preselected number of bits. The number of bits is selected in accordance with a predetermined number of bits required by a frame buffer, which thus establishes the number of color values supported by the graphics display system. In order to preserve accuracy to within the number of bits in each value in the frame buffer, the representation in the fixed-point engine includes additional bits relative to the number of bits in the color values sent to the frame buffer. Floating-point values received via the graphics API are converted to fixed-point representations by first prescaling the floating-point values.

Abstract: A method and apparatus for performing a block-write to a memory device comprising at least one register, a data input port, at least one memory bank, and a hardware device to block-write data from the register to the memory device, including receiving a first portion of block-write data from a data bus during a first half of a clock cycle; then, producing a second portion of the block-write data, and block-writing the first and second portions of the block-write data from a write logic unit to the memory bank at a double data rate as determined by the clock cycle.

Abstract: An apparatus and method for converting information from a text format to an audio format using distributed processing. A first set of computer readable program instructions receive information from a data source, convert the information from the text format to an intermediate format, and transmit the information in the intermediate format to a second data processor. A second set of program instructions, executable on the second data processor, are also included to convert the information from the intermediate format to the audio format. The first set of program instructions are executed on a remote, or server side, data processor, while the second set of program instructions are executed on a client side data processor. The first set of program instructions expand the information in the text format into phonemes using a grapheme to phoneme dictionary. The second set of program instructions convert the phonemes to audio output signals.

Abstract: The present invention discloses a method and system for testing imbedded logic arrays. An imbedded logic array is first tested for read/write functionality and then a test sequence is run to test the imbedded logic function. The method of the present invention writes a first data pattern to all addresses in an imbedded logic array. Next a second data pattern is written to a specific address followed by a read selecting all addresses concurrently. The output of the imbedded logic array, during this test, is the logic combination of the first data pattern and the second data pattern at the address where the second data pattern was written. By comparing the imbedded logic array output to an expected output the imbedded logic of the array is tested. The present invention anticipates imbedded logic arrays where the expected data output is not a previously written pattern.

Abstract: The present invention adds a programmable expect generator (PEG) that generates expected patterns of output for comparison to the actual outputs of an array while undergoing a complex test input sequence. The output of a programmable array built-in self test (PABIST) controller has its output increased to include separate control bits and a mask bit for a PEG. The PEG in one embodiment of the invention is substantially similar to a data control register that is programmed by a sequence of commands to generate the array input data patterns for testing an array. The program sequence that controls the PABIST and generates the input address, data and read/write patterns also outputs separate control bits to direct the PEG to generate expected outputs from the array when data from corresponding read addresses are read. The incorporation of a mask bit that accompanies each group of PEG control bits is used to inhibit the compare function that compares the output of the array to the output of the PEG.

Abstract: Servo control circuitry 300 includes a digital to analog converter 402 for converting digital servo control data into a pulse width modulated signal. A first conductor transmits the pulse width modulated signal to an external device 409. A second conductor transmits a reference signal derived from the clock signal to external device 409, external device 409 differentially receiving the pulse width modulated signal with respect to the reference signal.

Abstract: A device for testing flat panel displays includes an interface having compliant bumps mounted thereon, which make electrical contact with pads on the display panel. The interface may have a hole formed therein for allowing the passage of light therethrough when the interface is mounted on the display panel. The compliant bumps ensure that all of the bumps make sufficient electrical contact with the pads.

Abstract: A target detects the location of an impact of an object against a material by using various sensors. One utilization of the target is for a baseball or softball target whereby strikes and balls are detected depending upon the location of the impact of the ball against the target. The determination of the strikes and the balls is then provided to the thrower of the ball using some type of output device.

Abstract: Processing digital information made up of a plurality of n-bit samples is performed by raising each n-bit value to an x-bit value, x being greater than n. The x-bit values represent mid-band values, wherein in this context a band includes a sequential set of x-bit values having n most significant bits in common and a mid-band value is then an x-bit value approximately centered between the lowest and highest x-bit values of a band including that mid-band value. In some embodiments, the digital information may comprise video information. Thus, the process may be applied prior to converting the video information from a first color space (e.g., a red-green-blue (R-G-B) color space) to a second color space (e.g., a luminance-chrominance (Y-Cr-Cb) color space). For a particular embodiment, n may be equal to five or six, and x may be equal to eight, however, in general n may be variable amongst different ones of the samples.

Abstract: A memory clock generator apparatus and method are implemented. The memory clock is generated, “open loop,” from a processor clock. The processor clock is gated into, and propagated through a shift register. A set of outputs tapped off of the shift register is decoded, along with a plurality of control signals, in AND-OR logic to generate a clock output, which may run at a predetermined multiple of the memory clock rate. The clock output may have one of a plurality of ratios of memory clock period to processor clock period. The control signals select the ratio. The clock generator may be started asynchronously, and, additionally, the generator outputs a signal to the processor having an edge that has a predetermined temporal relationship with the start of the clock generator.

Abstract: A modular coating apparatus is disclosed which is adapted to couple to a host system, such as a cluster or in-line type coating system, as well as to operate in stand-alone fashion. The coating apparatus uses extrusion to initially deposit a film having a desired thickness. The substrate upon which the film is deposited may be spun to further distribute the film. Various embodiments of the coating apparatus are disclosed including embodiments utilizing a shim to mask the substrate and embodiments utilizing a rotatable chuck to facilitate cleaning of the substrate and/or the chuck. Preferably the various embodiments are sub-modules which may be interchanged in the main module as desired.

Abstract: A method and circuitry for linearly delaying a signal with linear delay steps. In one embodiment, circuitry in an integrated circuit for linearly delaying a signal comprises a plurality of control signals. The circuitry further comprises a fine delay element coupled to at least one of the plurality of control signals where the fine delay element comprises logic circuitry configured to provide fine adjustments to the delay of the signal. The circuitry further comprises at least one course delay element coupled to the fine delay element where the at least one course delay element is coupled to at least one of the plurality of control signals. Furthermore, the at least one course delay element comprises logic circuitry configured to provide course adjustments to the delay of the signal. The circuitry for linearly delaying a signal is configured to provide testability and programmability. The circuitry for linearly delay a signal is configured to provide linear delay steps.

Abstract: A method and apparatus mechanism for testing data processing devices are implemented. The test mechanism isolates critical paths by correlating a scanning microscope image with a selected speed path failure. A trigger signal having a preselected value is generated at the start of each pattern vector. The sweep of the scanning microscope is controlled by a computer, which also receives and processes the image signals returned from the microscope. The value of the trigger signal is correlated with a set of pattern lines being driven on the DUT. The trigger is either asserted or negated depending the detection of a pattern line failure and the particular line that failed. In response to the detection of the particular speed path failure being characterized, and the trigger signal, the control computer overlays a mask on the image of the device under test (DUT).

Abstract: Presented is a “high-order” Leading Zeros Anticipator or LZA circuit and specifically a five-input LZA. The prior-art two-input LZA circuit is part of almost all high-performance floating-point units or FPUs. The advantages of a high-order LZA (such as five-input) is that the LZA function may be started and finished sooner in the floating point pipeline, and therefore allows more time for other functions in the pipeline. Therefore, a high-order LZA, such as five-input LZA, may be faster than the prior art two-input LZA designs. Thus, speeding up the LZA function in a floating point pipeline may significantly increase the speed in which the overall floating-point unit may operate as compared to the prior-art two input LZA designs and may additionally inspire new floating-point michroarchitectures which may yield further performance gains.

Abstract: A cache model apparatus and method are implemented. A set of predetermined protocols for generating cache block movement events driving level one (L1) cache to level two (L2) cache traffic in a simulation environment are provided. An event protocol is selected for a test case in response to user input, or alternatively, a random selection is made. In accordance with the protocol selected, castouts of modified L1 cache lines are generated.

Abstract: The invention pertains to a coating apparatus and method in which most of the relative movement between a dispensing head and the substrate to be coated is provided by the coating head. The moving head configuration reduces the system footprint and diminishes leveling problems. A powered shuttle mechanism carries a dispensing head above a substrate to be coated while riding on a bearing located underneath the chuck holding the substrate thereby providing rigidity and reducing the system footprint. Chuck support is designed to accommodate anticipated vertical sag in the dispensing head by supporting the chuck at points along its periphery thereby permitting the chuck to sag in conjunction with the dispensing head. The shuttle mechanism is equipped with means for automatically adjusting the height of the dispensing head with respect to substrate to compensate for substrate placement error, substrate dimensional variation, and mechanical drift in the mechanical machine parts.