Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

Abstract: The present invention discloses a system and method for implementing instruction tracing in a computer system and in particular a computer system with a tightly coupled shared processor central processor unit (CPU). Each of the processors are generally purpose processors that have been modified by design to allow an instruction to execute and simultaneously to be stored and forwarded to shared memory operable as a trace buffer. Since each processor is general purpose, the trace routine necessary for tracing, can by one of the routines or programs that can be written and executed on either of the processors. One of the processors can run, collect and analyze the executed and store instructions of the other processor. Since the processors can be on a single chip the shared memory bus that writes and reads the executed instructions can operate at high speed.

Abstract: A method of compensating for finite common mode rejection in a switched capacitor circuit including arrays of input capacitors coupled to first and second differential nodes, includes the step of sampling a common mode voltage onto the differential nodes during a sampling phase. The input capacitors are then coupled to a ground node against which the common mode voltage is referenced to capture an offset voltage between the first and second differential nodes. The voltage offset is then subtracted out.

Abstract: A system for suppressing transient noise in switched-mode amplifier systems is disclosed. An amplifier, for amplifying a signal from a digital signal source includes a first complementary metal oxide semiconductor field effect transistor (MOSFET) pair. A common node of the pair is serially coupled to an output node of the amplifier by a resistor. The first MOSFET pair is configured to drive a ramp on the output node of the amplifier.

Abstract: A multicolor display element includes a plurality of display areas arranged in a pattern. Each display area includes three light emitting diodes for emitting light signals of respectively different colors. The light emitting diodes of the same color are commonly coupled to three buses, respectively, which may be activated in selective combinations by a gate network, to illuminate the display areas in a selective blended color.

Abstract: A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor.

Abstract: A level shifter 200 for shifting a logic high voltage of an input signal from a lower voltage to a higher voltage includes a latch 204 for storing a bit of data and having an output for driving a stored logic high bit at the higher voltage. A data node is coupled to a source of the higher voltage and an input of the latch. Voltage control circuitry 203 selectively gates the input signal received at the lower voltage with a bit of data stored in latch 204 and selectively pulls down the voltage at the data node in response.

Abstract: A frequency multiplication circuit is disclosed. The circuit includes a ring oscillator formed of an even number of phase shifting stages. Each phase shifting stage provides a high frequency output comprised of harmonics of the oscillation frequency of the oscillator. An input signal having a first frequency is injected into a feedback node of the oscillator, thereby injection locking the oscillator to the input signal such that the oscillation frequency of the oscillator is equal to the first frequency. An output signal is extracted from two of the phase shifting stages. One of the harmonic frequencies may be isolated in the output signal, thereby providing a clean output at a multiple of the input frequency. When the circuit is operated at high frequencies, the output signal consists substantially of the second harmonic frequency and the circuit operates as a frequency doubler.

Abstract: Device configuration processes operated within an operating system are run in parallel up until one or more new devices are detected. Once that occurs, the configuration process waits for current running processes to complete without starting new ones, and then re-runs the configuration processes needing to define new devices in the order they would have run if the entire operation had been performed serially. As a result, since most configurations processes will not be detecting new devices, they will run all the way to completion in parallel with others, thereby reducing system boot times. However, if a new device is discovered, it will be assigned the correct name with respect to the other devices.

Abstract: A charge pump has two charge pump nodes. The first charge pump node has a first current source (CS) with a source terminal connected to a positive supply voltage and an output terminal connected to the first charge pump node with a P channel metal oxide silicon transistor (PFET) controlled by a first control signal. The first charge pump node is also connected to a second CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a second control signal. The second charge pump node has a third CS with a source terminal connected to the positive supply voltage and an output terminal connected to the second charge pump node with a PFET controlled by a third control signal. The second charge pump node is also connected to a fourth CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a fourth control signal.

Abstract: An instrumentation circuit has an integrated circuit that has input terminals, an amplifier arrangement using feed forward compensation and an analog to digital converter and a serial data output receiving the output from said amplifier arrangement. A bridge circuit, having a transducer, or a thermocouple arrangement are connected to input terminals of the integrated circuit.

Abstract: An improved heavy oil conversion process is disclosed in which the heavy oil feed is first thermally cracked using visbreaking or hydrovisbreaking technology to produce a product that is lower in molecular weight and boiling point than the feed. The product is then deasphalted using an alkane solvent at a solvent to feed ratio of less than 2 wherein separation of solvent and deasphalted oil from the asphaltenes is achieved through the use of a two-stage membrane separation system in which the second stage is a centrifugal membrane.

Abstract: Instruction branching circuitry including a plurality of logical stacks each having a plurality of entries for storing an address for accessing a corresponding instruction in a memory device. A counter generates a pointer to an entry in an active one of the logical stacks, the counter including incrementation logic incrementing a stored pointer value following a Push operation and decrementation logic decrementing the stored pointer value following a Pop operation to the active one of the logical stacks. Selector circuitry selects the active one of the logical stacks in accordance with the performance of the Push and Pop operations.

Abstract: A burst transfer alignment apparatus and method are provided. An interface between the word-aligned subsystem and the double-word-aligned system bus loads a predetermined invalid bit pattern on the system bus corresponding to the second word of the double-word access, in response to a misaligned read. When execution of the predetermined invalid pattern is attempted, an execution exception is thrown. In response the cache line containing the invalid pattern giving rise to the exception is invalidated at the address of the invalid instruction data. Returning from the exception to the address of the invalid pattern, the cache line is refetched. The refetch occurs on an even word boundary, and therefore the refetched cache line transfers properly because the even word address coincides with a double word boundary expected by the bus system.

Abstract: A method and apparatus are implemented which allow applications to automatically resume from the last checkpoint on the receiver when a distribution interruption has occurred due, for example, to a network failure, machine reboot or power failure. For each repeater and endpoint the amount of data that must be received between two checkpoints may be preselected. Receivers flush the file buffers to nonvolatile storage when a checkpoint corresponding to an end of a data segment being transferred is reached. If a transmission is interrupted, the transfer is resumed from a beginning of the data segment being sent when the interruption occurred.

Abstract: An apparatus and method for power digital-to-analog converter protection are implemented. An attenuation value is set in response to the value of the supply voltage. The attenuation value is provided to a gain control, along with the input signal. A gain, offset by the attenuation value, determines the gain-adjusted output signal of the gain control generated from the input signal.

Abstract: A Self-Timed CMOS Static Circuit Technique has been invented that provides full handshaking to the source circuits; prevention of input data loss by virtue off interlocking both internal and incoming signals; full handshaking between the circuit and sink self-timed circuitry; prevention of lost access operation information by virtue of an internal lock-out for the output data information; and plug-in compatibility for some classes of dynamic self-timed systems. The net result of the overall system is that static CMOS circuits can now be used to generate a self-timed system. This is in contrast to existing self-timed systems that rely on dynamic circuits. Thus, the qualities of the static circuitry can be preserved and utilized to their fullest advantage.

Abstract: The present invention discloses a combination media and media station storage unit for storing a multiplicity of media elements along with a media station for the media elements. The combination unit allows a media station to be stored and secured for protection while allowing connections for signals and allowing controls for the media station to be accessed while it is in a stored and secure position. The combination media and media station storage unit also has removable lids that may contain optional features for adding functionality to the combination media and media station storage unit. These features include but are not limited to speakers, electronics for remote broadcast of playback information, electronics for remote control of the media station, batteries, windows for observing media station status, etc.

Abstract: A saturation select apparatus and method are implemented. Late stage logic blocks in an adder are provided which combine saturation select control signals with sum generating signals. A first saturation select control is asserted in response to an unsigned saturated instruction, and a second saturation select control is asserted in response to a signed saturated instruction. If either select control is asserted, each logic block outputs a corresponding bit of a respective saturation value. In response to a modulo mode instruction, both select control signals are negated, and each logic block outputs a corresponding bit of the arithmetic operation (sum or difference) implemented by the instruction.

Abstract: An amplifier is disclosed including multiple integrator stages. The amplifier includes a low-frequency path from a signal input to a signal output and relatively higher-frequency bypass paths around the first integrator stage. The paths converge at a summing node. To prevent instability when the integrators are saturated by large signals, the circuit includes a saturation detector which disables the relatively low-frequency paths during such saturation conditions.