Abstract: A method of cleaning a dual damascene structure. A first metal layer, a cap layer, and a dielectric layer are formed on a substrate in sequence. Then a dual damascene opening is formed in the dielectric layer and the cap layer, exposing the first metal layer. Then, a post-etching cleaning step is carried out to clean the dual damascene opening, and there are two types of cleaning methods. The first method uses a fluorine-based solvent to clean the dual damascene opening. An alternative cleaning method uses a hydrogen peroxide based solvent at a high temperature, followed by a hydrofluoric acid solvent cleaning step. Then, an argon gas plasma is sputtered to clean the dual damascene opening before a second metal layer fills in the dual damascene opening.

Abstract: A wrench having two driving stems pivotally connected with each other. One of the driving stems has a main stem and a female joint protruding from a rectangular or cylindrical section of the main stem with a hole at a center thereof. The other driving stem has the other main stem and a male joint projecting out of the center of a rectangular or cylindrical section of the main stem. The male joint and the female joint are engaged with each other via a coupler such as a roll pin. Therefore, without using an additional hinge or other mechanical coupler, these two driving stems are pivotally connected with each other.

Abstract: A double-triggered electrostatic discharge (ESD) protection circuit for coupling with a first voltage source and a second voltage source. The circuit includes a diode series and a transistor. The diode series comprises a plurality of serially connected diodes with the cathode of one diode connected to the anode of a subsequent diode. The positive terminal of the first diode in the diode series connects with the first voltage source. The gate terminal of the transistor connects with the anode of the last diode in the diode series. The substrate of the transistor connects with the cathode of the last diode in the diode series. The source terminal and the drain terminal of the transistor connect with the first voltage source and the second voltage source, respectively. By using double-triggered design, the ESD clamp device can be quickly triggered on to bypass ESD current.

Abstract: A method of conducting a laser repair operation. A silicon wafer has a plurality of chips thereon. Each chip has a plurality of bonding pads, a plurality of testing pads, a plurality of fuses and a passivation layer for protecting the chip. The passivation layer exposes the bonding pads and the testing pads. A bump-forming process is conducted to form a bottom metallic layer and a bump sequentially over each bonding pad. Only a bottom metallic layer is formed over each testing pad. The bumps axe formed, for example, by electroplating or printing. Testing is carried out by probing various bottom metallic layers above the testing pads. Finally, a laser repair is conducted.

Abstract: A method of conducting a laser repair operation. A silicon wafer has a plurality of chips thereon. Each chip has a plurality of bonding pads, a plurality of testing pads, a plurality of fuses and a passivation layer for protecting the chip. The passivation layer exposes the bonding pads an the testing pads. A bump-forming process is conducted to form a bottom metallic layer and a bump sequentially over each bonding pad. Only a bottom metallic layer is formed over each testing pad. The bumps are formed, for example, by electroplating or printing. Testing is carried out by probing various bottom metallic layers above the testing pads. Finally, a laser repair is conducted.

Abstract: A tape-out system of a mask tooling network for multiple supply chain. The tape-out system includes an integrated circuit (IC) designer computer, a design service computer, and a mask house computer; wherein the IC designer computer, the design service computer and the mask house computer are the multi-users for the tape-out system. A network connects the IC designer computer, the design service computer and the mask house computer. A device design data and a product mask data are provided through the network from the IC designer computer to the design service computer. The device design data and the product mask data undergo a processing step and a summarizing step, so that a product mask tooling data is obtained, which is then transmitted through the network to the mark house computer and the IC designer computer. The mask house computer fabricates a mask in accordance with the product mask tooling data.

Abstract: A method of correcting an optical mask pattern. A third pattern having a first strip-like pattern and a second strip-like pattern is provided. The first strip-like pattern attaches to the mid-section of the second strip-like pattern. A first modification step is conducted. A pair of assistant patterns is added to the respective sides of the first strip-like pattern to form a first modified pattern. A second modification step is conducted to shrink a portion of the first strip-like pattern to form a second modified pattern. Dimension in the reduced portion of the first strip-like pattern is a critical dimension of a main pattern. A third modification step is conducted using an optical proximity correction method. The second modified pattern is modified to a third modified pattern.

Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers. A cap layer, a low-k dielectric layer, a metal hard mask layer and a hard mask layer are formed in sequence on a provided substrate with metal wires. After patterning the metal hard mask layer and the hard mask layer to form a first opening, a fluid filling material layer is formed on the hard mask layer and fills the first opening. Using a patterned photoresist layer as a mask to define the filling material layer and the low-k dielectric layer, a second opening is obtained. After removing the photoresist layer along with the filling material layer, a damascene opening is formed by using the metal hard mask and the hard mask layers as a mask and the cap layer as an etching stop layer.

Abstract: Wood preservative compositions are disclosed. Treatment of lumber, plywood, and other wood products with a novel composition comprising the boron source composition, a melamine binder resin, and a urea casein activator resin protects lumber, plywood, and other wood products from attack by termites, fungi, fire and flame. The preservative can be formed by combining a source of boron such as boric acid and the water-soluble salts thereof, a melamine binder resin, and a urea casein resin. A wood preservative is characterized by a weight ratio of the urea casing activator resin to the melamine binder resin ranging from about 1:20 to 1:4 and a weight ratio of the boron source composition to the melamine binder resin ranging from about 1.3:1 to 9.6:1.

Abstract: An electrostatic discharge (ESD) protection device. The ESD protection device includes a first parasitic bipolar transistor, a second parasitic bipolar transistor, a third parasitic bipolar transistor and a fourth parasitic bipolar transistor formed over a substrate. A first longitudinal doped region is formed between the first parasitic bipolar transistor and the second parasitic bipolar transistor. Similarly, a second longitudinal doped region is formed between the third parasitic bipolar transistor and the fourth parasitic bipolar transistor. A guard ring circumscribes the substrate. An isolation region is formed inside the guard ring. The guard ring and the first/second longitudinal doped region are all connected to a ground terminal.

Abstract: A method of fabricating a self-aligned shallow trench isolation. A mask layer, two deep trenches and two internal electrodes of a capacitor are sequentially formed on a substrate. Two conductive layers are used to completely fill the two deep trenches. Then, two spacers are formed on exposed sides of the two conductive layers, and two doped regions are formed in a portion of the substrate located next to the two conductive layers. A patterned photoresist layer is formed to expose at least the spacers located in between the two deep trenches and the mask layer. The photoresist layer and the spacers are utilized as masks to etch away the exposed mask layer. The photoresist layer is utilized again as a mask to etch the exposed spacers and a portion of the exposed substrate. Sequentially, a remained portion of the photoresist layer and a portion of the conductive layers are removed. A remained mask layer is used as a mask to remove a portion of the exposed substrate, and a trench is thus formed.

Abstract: A process of forming an anti-fuse. First, an inter-metal dielectric layer, in which a funnel-shaped via is formed, is formed on a substrate. Next, a first conductive layer is formed over the substrate and filled into the funnel-shaped via. Subsequently, by, for example, a chemical mechanical polishing process, the first conductive layer outside the funnel-shaped via is removed to form a conductive plug. Afterward, an oxide chemical mechanical polishing process is performed to smooth the surface of the conductive plug. Next, a dielectric layer is formed on the top side of the conductive plug, and then a top plate is formed on the dielectric layer. Subsequently, an insulating layer is formed over the substrate, wherein the insulating layer is provided with a via and the via exposes the top plate. Finally, a second conductive layer is formed over the substrate and filled into the via.

Abstract: A method of fabricating a system on a chip device. On a substrate having a memory cell region and a peripheral circuit region a gate oxide layer and a polysilicon layer are formed. The peripheral circuit region can further be divided into a logic device region and a hybrid circuit region. A dielectric layer is formed on the peripheral circuit region. A cap layer and a conductive layer are further formed on the polysilicon layer in the memory cell region and on the dielectric layer in the peripheral circuit region. Using the dielectric layer in the peripheral circuit region and the gate oxide layer in the memory cell region as etch stop, the cap layer and the conductive layer in the peripheral circuit region, and the cap layer, the conductive layer and the polysilicon layer are patterned. As a result, at least a gate and a top electrode are formed in the memory cell region and the hybrid circuit region, respectively.

Abstract: A method for manufacturing low cost electroluminescent (EL) lamps is disclosed. The method of the present invention includes the first step of die cutting, embossing or chemically etching the metal foil surface of a metal foil bonded flexible electrical insulation to simultaneously form one or more rear capacitive electrodes, electrical terminations, optical registration fiducial indicia, and a continuous carrier means that is then coupled to a precisely positioned indexing system. Next, the rear metal foil capacitive electrodes are coated with a capacitive dielectric layer precisely isolating the rear electrode form. In the third step, a layer of electroluminescent phosphor ink is applied to the rear capacitive electrodes to precisely form areas of illumination. In step four, a layer of light transmissive and electrically conductive ink is applied to cover the EL phosphor layer.

Abstract: A fabrication method for a CMOS image sensory device is described. An isolation layer is formed in the substrate to isolate a photodiode sensory region and a transistor device region. A gate structure is further formed on the transistor device region, followed by forming concurrently a source/drain region in the transistor device region beside the side of the gate structure and a doped region in the photodiode sensory region. Thereafter, a self-aligned block is formed on the photodiode sensory region, followed by forming a protective layer on the substrate.

Abstract: A structure of an ESD protection circuit device located under a pad, protecting an internal circuit and a method of manufacturing the same are disclosed. The ESD protection circuit device having a pad window, located under a pad, includes a semiconductor substrate having a P-well and an N well. The P-well and the N-well have an interface. A predetermined area, pad window is selected in the substrate. A first STI structure, a second STI structure and a third STI structure are formed in the substrate within the pad window. N-type doped regions are formed P-well and in the N-well. First p-type doped regions are formed in the P-well and in the N-well and second p-type doped regions are formed in the P-well and in the N-well. A first zener diode is formed in the N-well and a second zener diode is formed in the P-well.

Abstract: A device for locally shielding or blocking a user from close proximity electromagnetic fields emitted by a wireless transmit/receive electronic equipment antenna 22 such as a cellular telephone. The device includes a wearable garments such as a baseball cap 10, electronic carrying pouch 110, fan 210, 250, 410, eyeglass 610, or screens, joined with having EMI/RFI material properties that is specifically worn by the user or placed between the user and the electromagnetic field emanating wireless antenna source 22. It serves to provide as a electromagnetic field shield, either reflective, absorptive, or dissipative behavior in nature, from an direct line-of-sight electromagnetic field radiating from a wireless device antenna 22.

Abstract: A fabrication method for a low dielectric constant (k) material layer is described. A high molecular weight material layer is formed on a substrate. The high molecular weight material layer is then cured. A bonding material layer is formed on the high molecular weight material layer, wherein a major component in the bonding material layer is an organic compound, wherein the organic compound has a silicon-containing moiety and an unsaturated hydrocarbon moiety. The bonding material layer is further cured, allowing the organic silicon compound to cross-link within the high molecular weight material layer to form a high molecular weight material layer with a silicon rich surface. Moreover, the curing for the high molecular weight material layer and for the bonding material layer can conduct concurrently.

Abstract: An optical proximity correction method that uses additional corner serifs or hammerhead pattern to correct and avoid pull up of ends in a main pattern. These corner serifs are set such that the main pattern is corrected with only a slight line-end width expansion and line-end approaching the original design in length. Since the optical proximity correction method is able to correct the main pattern so that the end approaches the original design after a photo-exposure, any misalignment that may lead to uncompleted contact or an open of metallic interconnects can be avoided. Furthermore, the slightly expanded end permits a higher process window in the fabrication of metallic interconnects.

Abstract: A method of figuring an exposure energy. A required exposure energy is calculated according to a critical dimension (CD) of an exposing layer. A first CD deviation is obtained from a layer before the exposing layer. From the first CD deviation, a first energy compensation is calculated. Whether the deviation of photoresist sensitivity of two sequential batches is less than 1% is checked. If the deviation of photoresist sensitivity of two sequential batches is less than 1%, a sum of the required exposure energy and the first energy compensation is the exposure energy applied to the exposing layer. Otherwise, a second CD deviation is commutated according to the deviation of photoresist sensitivity of two sequential batches. A second energy compensation is then obtained from the second CD deviation, and a sum of the required exposure energy and the first/second energy compensation is the exposure energy applied to the exposing layer.