Abstract: The invention provides methods and systems for laser assisted wirebonding. One or more conditioning laser pulses are used to prepare a bonding surface for wirebonding by removing impurities such as residues from manufacturing processes, oxides, or irregularities on the bonding surface. Subsequently, a free air ball is brought into contact with the conditioned bonding surface to form a weld.

Abstract: An embodiment of the present invention includes a method of providing a non-uniform distribution of decoupling capacitors to provide a more uniform noise level across the chip. Leads on a packaged semiconductor chip are grouped into two or more regions. Types of leads needing decoupling capacitors are grouped into lead categories. For each region, there may be one or more lead categories therein. One or more decoupling capacitors are preferably assigned to each lead category in each region. Calculations may be performed to estimate a desired capacitance for each decoupling capacitor for each lead category in each region. When a chip has different components operating at different switching frequencies, different voltages, and/or different switching currents, the distribution of the decoupling capacitors will likely be non-uniform to provide a more uniform noise level across the chip, as compared to a uniform distribution of decoupling capacitors for the chip.

Abstract: One embodiment of the present invention includes a method for reactively cleaning a contact mechanism. The method includes measuring contact resistance (CRES) associated with a plurality of electrical contacts of the contact mechanism. The method also includes generating at least one statistic of the measured CRES associated with the plurality of electrical contacts of the contact mechanism, and comparing the at least one statistic of the CRES associated with the plurality of electrical contacts of the contact mechanism with at least one CRES threshold parameter associated with an unacceptable level of CRES. The method further includes cleaning the plurality of electrical contacts of the contact mechanism based on the comparison of the at least one statistic of the CRES and the at least one CRES threshold parameter.

Abstract: The preferred embodiments of the present invention provide non-invasive approaches of testing ICs that use photon emission from semiconductor devices to provide results of various testing procedures. For example, instead of reading the results from the built-in-self-test (BIST) circuitry using micro-mechanical probes, the results from BIST may be represented using an array of circuit elements configured to emit photons. Accordingly, by reading the photon emission of this BIST circuitry, the results of the testing procedures may be measured non-invasively. In addition, the preferred embodiments also may use an external light source to initiate on-chip testing functions so that the number of external connections to the IC may be further minimized. For example, instead of providing input signals to BIST circuitry using micro-mechanical probes, pulsed lasers may provide desired input signals.

Abstract: Semiconductor chip (1101) of a ball grid array device (1100) is mounted onto tape substrate (1102) using attach adhesive (1103). The metal layer on the top surface of substrate (1102) uses between about 30% to 90% of its area for connecting lines (1104), and only the remainder for members/rings (1105) and terminals (1106). Routing of differential pair signals and large numbers of signals on a single layer tape package are feasible. This embodiment creates an inexpensive high performance tape ball grid array package for chip-scale devices. Terminals (1106) serve the connection (by bonding wires or reflow bumps) to the chip contact pads. Inserted in members/rings (1105) are the conductive pins (1107), which serve as anchors for the solder bodies/balls (1108). Pins (1107) are substantially insensitive to the thermomechanical stresses, which occur in device (1100) during assembly, testing and operation.

Abstract: A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is substantially coplanar with the chip, without warpage. One of the chip sides is attached to the first substrate surface using adhesive material (504), which has a thickness. The thickness of the adhesive material is distributed so that the thickness (504b) under the central chip area is equal to or smaller than the material thickness (504a) under the peripheral chip areas. Encapsulation compound (701) is embedding all remaining chip sides and the portions of the first substrate surface, which are not involved in the chip attachment. When reflow elements (720) are attached to the substrate contact pads, they are substantially coplanar with the chip.

Abstract: The objective of the invention is to provide a semiconductor device manufacturing method that can suppress the formation of voids in the underfill resin and realize a highly reliable flip-chip assembly. The semiconductor device manufacturing method pertaining to the present invention comprises the following processing steps: a step of operation in which a plurality of electrodes 24, formed in a two-dimensional array on a principal surface 22 of semiconductor chip 20, are connected to corresponding conductive regions 32, 34 on substrate 30, a step of operation in which underfill resin 40 is supplied between the principal surface of the semiconductor chip and the substrate, and a step of operation in which the semiconductor chip and substrate with supplied underfill resin 40 are exposed to atmospheric pressure.

Abstract: A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated and having a plurality of electrical coupling members, and an insulating underfill material. The method comprises the steps of positioning a wafer having a plurality of integrated circuits, including the coupling members, in a vacuum chamber of a plasma apparatus so that the polymer-coated surface faces the plasma source. Next, a plasma is initiated; the ion mean free path is controlled so that the ions reach the wafer surface with predetermined energy. The wafer surface is then exposed to the plasma for a length of time sufficient to roughen the polymer surface, clean the polymer surface from organic contamination and improve the surface affinity to adhesion. The adhesion ability of this surface to organic underfill material is thus enhanced.

Abstract: In certain embodiments, a leadframe structure for forming one or more integrated circuit packages includes a number of adjacent substantially parallel lead bars adapted to receive a die associated with an integrated circuit at one or more of the lead bars such that the one or more lead bars extend from opposite sides of the die. The leadframe structure also includes one or more support structures (e.g. lead support bars 26) adapted to help hold the lead bars together.

Abstract: A system for testing a device includes a processor that operates to execute instructions, where the instructions are used to test a device. The processor also operates to generate test signals associated with the test instructions. An interface apparatus is coupled to the processor and operates to communicate the test signals to the device. The interface apparatus includes connectors, where each connector operates to communicate at least one of the test signals.

Abstract: Disclosed herein is an improved method and apparatus for simultaneously performing tests on several devices at the same time. An aspect of one embodiment of the invention is an improved DMA controller that automatically selects certain pin groups, which are connected to a common data bus, to receive test data words from a common data bus. By selecting more than one pin group at the same time, test data (such as a test data word) can be simultaneously loaded onto multiple pin cards at the same time. By loading this data into multiple pin cards at the same time, test data can be “fanned-out” to multiple pin cards and thereby be sent to multiple device sites at the same time. Another aspect of one embodiment of the invention utilizes DMA-based hardware to select which pin groups should received “fanned-out” test data. By utilizing DMA-based hardware to fan-out the test data, the software-based test programs and patterns may be created to manipulate a single device.

Abstract: A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (302) and a plurality of lead segments (303). Covering the base metal are, consecutively, a continuous nickel layer (201) on the base metal, a layer of palladium on the nickel, wherein the palladium layer (203) on the chip side of the structure is thicker than the palladium layer (202) opposite the chip, and a gold layer (204) on the palladium layer (202) opposite the chip. A semiconductor chip (310) is attached to the chip mount pad and conductive connections (312) span from the chip to the lead segments. Polymeric encapsulation compound (320) covers the chip, the connections, and portions of the lead segments, but leaves other segment portions available for solder reflow attachment to external parts.

Abstract: An apparatus comprising an insulating substrate having first and second surfaces and a plurality of metal-filled vias extending from the first to the second surface. The first and second surfaces have contact pads, each one comprising a connector stack to at least one of the vias. The stack comprises a seed metal layer in contact with the via metal capable of providing an adhesive and conductive layer for electroplating on its surface, a first electroplated support layer secured to the seed metal layer, a second electroplated support layer, and at least one reflow metal bonding layer on the second support layer. The electrolytic plating process produces support layers substantially pure (at least 99.0%), free of unwanted additives such as phosphorus or boron, and exhibiting closely controlled grain sizes. Reflow metal connectors provide attachment to chip contact pads and external parts.

Abstract: A semiconductor device with a chip having at least one metallic bond pad (101) over weak insulating material (102). In contact with this bond pad is a flattened metal ball (104) made of at least 99.999% pure metal such as gold, copper, or silver. The diameter (104a) of the flattened ball is less than or equal to the diameter (103a) of the bond pad. A wire (110) is connected to the bond pad so that the wire has a thickened portion (111) conductively attached to the flattened metal ball. The wire is preferably made of composed metal such as gold alloy. The composition of the flattened ball is softer than the wire. This softness of the flattened ball protects the underlying insulator against damage caused by pressure or stress, when the composed ball is attached.

Abstract: Disclosed are integrated circuit assemblies with increased stand-off height and methods and systems for their manufacture. Methods of the invention provide for assembling a semiconductor device by aligning a die with a substrate and interposing solder between corresponding substrate and die bond pads. A lifting force is applied to the die during heating of the solder to a liquescent state, thereby increasing the stand-off height of the die above the substrate. The lifting force is maintained during cooling of the solder to a solid state, thereby forming increased stand-off height solder connections.

Abstract: A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips (202, 203) have a dimension (220, 230) narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (224, 234). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate (204) has terminals and reflow bodies (242) to connect to the studs of the projecting interposer.

Abstract: An integrated circuit package lead frame, comprising a plurality of leads and a spine electrically connected to said plurality of leads, said spine comprising indentations between a pair of said leads. The indentations prevent the pair of leads from becoming electrically connected to each other after a singulation process.

Abstract: A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the trench, which serves as a low-resistance contact to the back side of the device. In another embodiment, the trench-fill material is separated from the device by an insulating layer, and serves as a back gate structure.

Abstract: A programmable delay circuit is provided in either data input path or a clock input path of a sequential element contained in a scan chain of an integrated circuit. The scan chain is used to test the integrated circuit using a sequential scan technique (e.g., Automatic test pattern generation (ATPG)). Due to the programmability of delay magnitude, the burden on a designer to achieve synchronization of the data input with the clock signal while testing, is reduced.

Abstract: A semiconductor device having a leadframe comprised of a base metal (110, e.g., copper), a chip mount pad (103) and a plurality of lead segments (104). Each of the segments has a first end (104a) near the mount pad and a second end (104b) remote from the mount pad. The device further has a semiconductor chip (103) attached to the mount pad and electrical interconnections (107) between the chip and the first segment ends. Encapsulation material (120) covers the chip, the bonding wires and the first segment ends, yet leaves the second segment ends exposed. At least portions of the second segment ends have the base metal covered by a layer of solderable metal (130, e.g., nickel) and by an outermost layer of noble metal (140, e.g., stack of palladium and gold).