Patents Assigned to A & A Corporation
  • Patent number: 6724647
    Abstract: A semiconductor integrated circuit (FPLA) having a desired logical function achieved by arranging on a semiconductor chip variable logical circuits each having n×n (e.g., four) memory cells alternatively selected according to a combination of n (e.g., two) pairs of positive and negative phase signals and provided to output the positive and negative phase signals according to the data stored in the selected memory cell, variable wiring unit provided with signal lines for inter-connecting the variable logical circuits and switching elements for connecting/disconnecting signal lines inter-secting to each other, a wiring connection state storage memory circuit where the states of the switching elements are stored.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: April 20, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Masayuki Sato, Isao Shimizu, Hideaki Takahashi, Yoshikazu Saitoh
  • Patent number: 6724841
    Abstract: The present invention proposes a method for processing signals in order to remove waveform distortion by using an equalizer, said method comprising the steps of receiving an incoming signal, preprocessing said incoming signal, estimating a channel impulse response from said received signal estimating a noise energy from said received signal, calculating filter taps by using said estimated channel impulse response and said noise energy, filtering said received signal by using said calculated filter taps by a feedforward filter means, and supplying said received signal to an equalizer means which comprises a feedback filter, to obtain a resulting signal by a decision in said equalizer means, wherein said estimated channel impulse response is partitioned into at least two parts, in said calculating step of the filter taps one of said parts of said channel impulse response being used for calculating filter taps in said calculating step of the filter taps by using a weight function.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: April 20, 2004
    Assignee: Nokia Corporation
    Inventor: Olli Piirainen
  • Patent number: 6724767
    Abstract: Systems and methods for queuing and de-queuing packets in a two-dimensional link list data structure. A network processor processes data for transmission for a plurality of Virtual Connections (VCs). The processor creates a two-dimensional link list data structure for each VC. The data field of each data packet is stored in one or more buffer memories. Each buffer memory has an associated buffer descriptor that includes a pointer to the location of the buffer memory, and a pointer pointing to the memory of the next buffer descriptor associated with a buffer memory storing data for the same packet. Each data packet also has an associated packet descriptor including a pointer pointing to the memory location of the first buffer descriptor associated with that packet, and a pointer pointing to the memory location of the packet descriptor associated with the next data packet queued for transmission.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: April 20, 2004
    Assignee: Intel Corporation
    Inventors: Simon Chong, Anguo Tony Huang, Man Dieu Trinh
  • Patent number: 6725223
    Abstract: A storage format and methods for improving the performance of the symbol table of an encoded vector index. The symbol table comprises a hash table, entries of the hash table storing associated key values and codes for the encoded vector index. Hash table entries store an accumulated count of occurrences of prior and the current key values, which improves the efficiency of responding to a request for a key range count. A binary radix tree is used to locate entries, which comprises a plurality of nodes, corresponding to binary digits of a binary representation of a key value. Codes are assigned to key values for the encoded vector index in a distributed fashion, so there are available code values between existing code values in the code ordering, that can be assigned to new key values, alleviating the need to reorganize the code values upon an insertion.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: April 20, 2004
    Assignee: International Business Machines Corporation
    Inventors: Abdo Esmail Abdo, Kevin James Kathmann, Kurt Walter Pinnow
  • Patent number: 6722948
    Abstract: A modification to a chemical mechanical polishing conditioner of a type having a member with a conditioning surface adapted to apply a force to and condition a polishing pad. The conditioner includes at least one sensor disposed within the member, where the at least one sensor is adapted to sense at least one of an amount of the force applied to the polishing pad and a uniformity across the member of the force applied to the polishing pad. In this manner, the force applied by the conditioner to the pad, and the uniformity of the force applied by the conditioner to the pad, can be sensed. These sensed forces can be monitored, reported, and controlled, thus providing a better controlled chemical mechanical polishing process.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventor: Michael J. Berman
  • Patent number: 6725396
    Abstract: Described is a method for isolating faults to a correct field replaceable unit (FRU) of a data processing system. When a processor timeout occurs, a fault isolation logic is triggered and checks the boot record to determine if the timeout occurred because of an FRU fault before or after the service processor completed its system initialization. When the timeout occurred because of fault that occurred while the service processor was loading operating system (OS) (e.g., AIX) instructions from the boot device in the input/output (I/O) subsystem, then the FRU callout indicates a boot fault associated with the I/O planar and the CPU (processor) card. When the FRU fault occurred prior to fetching the OS instructions from the boot device or after the service processor completed its system initialization procedures, then the FRU callout is attributed to the processor card and backplane. Attributing boot error faults to incorrect FRUs is therefore substantially eliminated.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: April 20, 2004
    Assignee: International Business Machines Corporation
    Inventors: George Henry Ahrens, David Russell Armstrong
  • Patent number: 6723072
    Abstract: A device for delivering fluid, such as insulin, to a patient. The device includes an exit port assembly, a syringe-like reservoir including a side wall extending along a longitudinal axis towards an outlet connected to the exit port assembly, and a plunger assembly received in the reservoir. The plunger assembly includes a two-way shape memory element connecting first and second lateral segments, and having a changeable length decreasing from an uncharged length to a charged length when at least one charge is applied to the shape memory element. Successively applying a charge and removing the charge from the two-way shape memory element causes longitudinal movement of the plunger assembly towards the outlet of the reservoir in order to cause fluid to be dispensed from the reservoir to the exit port assembly.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: April 20, 2004
    Assignee: Insulet Corporation
    Inventors: J. Christopher Flaherty, Christopher Carter Gregory, Derek Dwayne Mahoney, John Michael Margicin
  • Patent number: 6724727
    Abstract: The present invention provides a method and apparatus for a communications system that prioritizes packets that are transmitted over a digital communication channel utilizing at least one error-correcting transmission path associated with a Quality of Service (QoS) objective. The QoS objective is used to select the appropriate transmission path (that may include forward error coding, scrambling, and interleaving) that satisfies the relevant metrics of the desired level of service quality such as packet latency, variation of the packet latency, information throughput, and packet error rate (PER). The communications system selects a transmission path that is associated with QoS objectives best matched to the QoS objectives as required by the originating application.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: April 20, 2004
    Assignee: Nokia Corporation
    Inventor: Raymond Counterman
  • Patent number: 6724957
    Abstract: It is an object of the present invention to provide an optical filter which allows parameters to be easily adjusted, which allows birefringence and temperature dependence to be easily compensated for, and which is essentially free from dispersion. The optical filter includes an optical coupler that splits light into two beams, optical couplers connected to outputs of the optical coupler, a first group of two optical waveguide delay lines connected to the coupler, a second group of two optical waveguide delay lines connected to the coupler, an optical coupler that combines lights from the first group of the lines, an optical coupler that combines lights from the second group of the lines, and a multimode interference optical coupler that combines lights from the couplers together.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: April 20, 2004
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Takashi Saida, Takayuki Mizuno, Akira Himeno, Katsunari Okamoto, Koichi Takiguchi, Manabu Oguma
  • Patent number: 6724320
    Abstract: There is provided a system and method for controlling at least one traffic light having a vehicle having a transmitter and a receiver for transmitting and receiving traffic control signals, and a control unit for processing traffic control signals; and a traffic control module having a transmitter and a receiver for transmitting and receiving traffic control signals, a control unit for processing traffic control signals, traffic light control logic for controlling the at least one traffic light, and means to connect to the at least one traffic light; wherein the traffic control signals control the flow of traffic about the at least one traffic light enabling a vehicle to travel from a present location to a destination passing through intersections at which traffic flow is controlled by the at least one traffic light; and also including means for controlling at least one traffic light on a selected optimal route in response to the traffic control signals.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: April 20, 2004
    Assignee: International Business Machines Corporation
    Inventors: Sara H. Basson, Dimitri Kanevsky, Wlodek W. Zadrozny
  • Patent number: 6725389
    Abstract: A method of clock buffer placement for minimizing clock skew includes the steps of (a) constructing a trunk delay model for a plurality of clock cells within a partitioning group, (b) placing a clock buffer at an initial location in the trunk delay model, (c) estimating a clock skew and an insertion delay from the trunk delay model, (d) checking whether the clock skew exceeds a clock skew limit, and (e) if the clock skew exceeds the clock skew limit, then selecting a new location for the clock buffer in the trunk delay model.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Alexander Tetelbaum, Rajiv Kapur
  • Patent number: 6718416
    Abstract: An example embodiment of a computer system that includes a removable agent that can be removed or installed without powering down the system includes a fixed bus agent and the replaceable bus agent. The fixed bus agent and the replaceable bus agent are electrically coupled together by a presence detect signal, a synchronization signal, and a data bus. A deassertion of the presence detect signal indicates to the fixed bus agent that the removable bus agent has been disconnected and is no longer electrically coupled to the fixed bus agent. The fixed bus agent then tri-states its outputs and also prevents potentially invalid data from being delivered to the core circuitry of the fixed bus agent. An assertion of the presence detect signal indicates to the fixed bus agent that the replaceable bus agent is electrically connected to the fixed bus agent. In response to the assertion of the presence detect signal, the fixed bus agent and the replaceable bus agent enter reset periods.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: April 6, 2004
    Assignee: Intel Corporation
    Inventors: Keith M. Self, Matthew B. Haycock
  • Patent number: 6716957
    Abstract: A bioabsorbable material such as a terpolymer of poly-(L-lactide/D-lactide/glycolide). The material may consist of 85 molar percent L-lactide, 5 molar percent D-lactide, and 10 molar percent glycolide. The material may have a heat of fusion of about 15-25 J/G, tensile strength retention at 26 weeks of incubation of at least about 50%, and tensile strength retention at 52 weeks of incubation of at most about 25%. The material may be used in implantable devices such as bone fixation devices.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: April 6, 2004
    Assignee: Stryker Technologies Corporation
    Inventor: Deger C. Tunc
  • Patent number: 6717557
    Abstract: An AC type plasma display is provided with first and second substrates disposed oppositely. Scan electrodes and sustainment electrodes are provided alternately at an opposite face side to the second substrate in the first substrate, the scanning and sustainment electrodes extending in a row direction. Data electrodes are provided at an opposite face side to the first substrate in the second substrate, the data electrodes extending in a column direction. Auxiliary electrodes are provided at all of spaces between the scan electrodes and the sustainment electrodes. The auxiliary electrodes extend in a row direction.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: April 6, 2004
    Assignee: NEC Corporation
    Inventor: Mitsuhiro Ishizuka
  • Patent number: 6715401
    Abstract: During a normal brake operation, a brake reaction from a reaction disc is transmitted to a valve plunger through an outer plunger and an inner plunger. During an emergency brake operation, as a valve plunger is driven forward through a given stroke relative to a valve body, a tubular member retracts relative to the valve body. In a servo balance condition, which is reached subsequently, the valve plunger, retracts by an amount corresponding to the retraction of the tubular member, and the outer plunger abuts against a holder. A brake reaction from the reaction disc is transmitted to the valve plunger only through the inner plunger, allowing a booster ratio to be greater and a jumping quantity to be greater than during a normal brake operation. It is possible to increase an output from a brake booster 1 rapidly in immediate response to a quick depression of a brake pedal.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: April 6, 2004
    Assignee: Bosch Automotive Systems Corporation
    Inventors: Yoshiyasu Takasaki, Hidefumi Inoue
  • Patent number: 6715497
    Abstract: A method and apparatus are provided for eliminating contaminants including metallic and/or hydrocarbon-containing contaminants on a surface of a semiconductor substrate by heating a semiconductor substrate which may have contaminants on the surface thereof to an elevated temperature within an integrated closed system while simultaneously purging the integrated closed system with a chlorine-containing gas. At the elevated temperatures the chlorine dissociates from the chlorine-containing gas and reacts with the contaminants on the substrate surface to form volatile chloride byproducts with such contaminants which are removed from the integrated closed system while the substrate is continuously heated and purged with the chlorine-containing gas. Subsequently, the substrate is moved to a cooling chamber within the integrated closed system and cooled to provide a semiconductor substrate having a clean surface.
    Type: Grant
    Filed: January 2, 2001
    Date of Patent: April 6, 2004
    Assignee: International Business Machines Corporation
    Inventors: Brian P. Conchieri, David D. Dussault, Mousa H. Ishaq
  • Patent number: 6716501
    Abstract: This invention relates to a multilayered film for use as in-mold label, comprising: a core layer having a first surface and a second surface, the core layer being comprised of a polymeric material and particulate solids dispersed in the polymeric material; and a first skin layer overlying the first surface of the core layer; the film being formed by co-extruding the core layer and first skin layer to form the multilayered film, hot-stretching the film at a temperature above the expected service temperature of the label to provide the film with a machine direction orientation, the density of the film being reduced by about 5% to about 25% during hot-stretching, and annealing the film at a temperature above the expected service temperature of the label; the film having a machine direction Gurley stiffness value in the range of about 30 to about 120, a machine direction shrinkage of less than about 2%, and a machine direction shrink tension at 200° F. (93.3° C.) of less than about 100 psi.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: April 6, 2004
    Assignee: Avery Dennison Corporation
    Inventors: John Kovalchuk, Bernard S. Mientus
  • Patent number: 6716747
    Abstract: When a hole pattern is formed on a film to be processed, a matching deviation margin at a lithography step is reserved by making a diameter of a bottom of a hole substantially equal to a diameter of an aperture of the hole. The method for manufacturing the semiconductor apparatus includes the steps of: forming a (first) mask material film on a film to be processed; forming a tapered open pattern on the (first) mask material film; and etching the film to be processed by using the (first) mask material film as a mask.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: April 6, 2004
    Assignee: Sony Corporation
    Inventor: Fumikatsu Uesawa
  • Patent number: 6717320
    Abstract: The slip ring device (10) includes stationary and rotary members (11, 20) rotatable to each other. The slip ring device includes a sliding contact system for electrically interconnecting the stationary and rotary members. The sliding contact system includes slip rings (30, 31) with sliding faces (34a, 35a) mounted to one of the stationary and rotary members. The slip rings are separated from each other, with the sliding faces facing each other. The sliding contact system includes sliding contact members (17, 18) mounted to the other of the stationary and rotary members. Each of the sliding contact members slidably contact with each of the sliding faces.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: April 6, 2004
    Assignee: Yazaki Corporation
    Inventors: Hideki Adachi, Kazuto Nakamura
  • Patent number: 6718506
    Abstract: Speed of operation is increased in a DVD error correcting apparatus by first correcting rows of DVD data from PI check bytes in a PI engine and storing it in SRAM and feeding the corrected PI data into SDRAM and a PO engine, where only the syndromes are stored in an 8K SRAM, and only the bytes to be corrected are written to SDRAM. Speed of operation is enhanced by transferring most of the random and small burst of data to SRAM in big bursts with a minimum number of random accesses to the main SDRAM or DRAM.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: April 6, 2004
    Assignee: Zoran Corporation
    Inventors: Jos Sebastian, Chen-Chi Chou