Abstract: A protection circuit includes: an NMOS transistor, including a first end (source), a second end (drain), and a control end (gate), the first end being connected with a first end of a current path formed by parasitic diodes of a semiconductor element included in an internal circuit, and the second end being connected with a GND terminal; and a current limiting circuit, connected in parallel with the NMOS transistor.

Abstract: A vertical Hall element includes: an N-type epitaxial layer formed on a surface of a P-type semiconductor substrate; a first electrode group disposed on a surface of the N-type epitaxial layer and formed of three or more electrodes; and a P-type high-resistance diffusion layer disposed in a ring shape on an outer periphery separated from the first electrode group and including a second electrode group capable of being applied with a voltage such that an electric field with respect to the first electrode group becomes constant.

Abstract: An ultrasonic device includes: a plurality of oscillation elements to generate ultrasonic waves toward a subject, and generate voltages according to ultrasonic waves reflected by the subject; a data generator to generate a predetermined number of sets of time-series data, each of the sets indicating change in time in a plurality of voltages generated by a predetermined number of oscillation elements, among the voltages generated by the plurality of oscillation elements; a data accumulator to accumulate the sets of time-series data generated by the data generator; a selector to select time-series data from among those generated by the data generator or those accumulated in the data accumulator; a data processor to generate image data by processing a predetermined number of sets of the selected time-series data; and a controller to cause the data generator to stop generating time-series data while the selector selects the accumulated time-series data.

Abstract: A voltage detection circuit 101 includes: a bleeder resistance circuit BR, dividing the battery voltage into divided voltages VD1 and VD2; a comparator C2, receiving the divided voltage VD1 and a reference voltage VREF and outputting a signal indicating a normal state or an overcharge state; a switch M3, connected in parallel with a resistor part R2 and turned on in the overcharge state; a comparator C1, receiving the divided voltage VD2 and the reference voltage VREF and outputting a signal indicating the normal state or a low-voltage state; a switch M1, connected between a high-voltage side of a resistor part R3 and an input part of the comparator C1 and turned on in the low-voltage state; and a switch M2, connected between a low-voltage side of the resistor part R3 and the input part of the comparator C1 and turned off in the low-voltage state.

Abstract: A voltage divider circuit includes: a first terminal; a second terminal; a voltage divider output terminal; a first resistance group in which multiple resistance elements are connected between the first terminal and the voltage divider output terminal; a second resistance group in which multiple resistance elements are connected between the second terminal and the voltage divider output terminal; a first metal film connected to the first terminal and covering a region including at least a part of the first resistance group in plan view; and a second metal film connected to the second terminal and covering a region including at least a part of the second resistance group in plan view, and the second metal film further covers a part of the first resistance group.

Abstract: A voltage regulator includes: an output transistor containing a source connected to an input port and a drain connected to an output port; voltage dividing resistors which are connected between a voltage adjustment port and a ground port, divide an adjustment voltage received at the voltage adjustment port, and output a feedback voltage; a reference voltage circuit which outputs a reference voltage; an error amplifier circuit which controls a gate voltage of the output transistor based on the reference voltage and the feedback voltage; and a disconnection protection circuit which includes a first MOS transistor containing a source connected to the output port and a gate connected to the voltage adjustment port, and detects a disconnection of a bonding wire of the voltage adjustment port.

Abstract: Operational instability is prevented without compromising the state transition speed. A mask control circuit is a circuit which generates a mask signal masking a control signal during a period in which a voltage level of a monitoring target terminal to be monitored is transitioning. The mask control circuit includes: a first input port which receives a signal supplied to the monitoring target terminal; a second input port which receives a signal representing the voltage level of the monitoring target terminal; a logic circuit which determines whether the voltage level of the monitoring target terminal is in transition based on signals received from the first input port and the second input port; and an output port which outputs a signal indicating a determination result of whether the voltage level of the monitoring target terminal is in transition as the mask signal.

Abstract: A voltage follower circuit includes a first MOS transistor which has a source connected to an input port, a second MOS transistor which has a source connected to an output port and has a gate and a drain connected to a gate of the first MOS transistor, a first constant current source connected between a drain of the first MOS transistor and a second power supply terminal, a second constant current source connected between the drain of the second MOS transistor and the second power supply terminal, and a depletion type third MOS transistor which has a gate connected to the drain of the first MOS transistor, has a drain connected to a first power supply terminal, and has a source connected to the output port.

Abstract: A charge/discharge control circuit controls charging and discharging using a discharge control FET which opens and closes a discharge path and a charge control FET which opens and closes a charge path. The charge/discharge control circuit includes a charge/discharge monitoring circuit; and a control circuit, turning on and off the discharge control FET connected between a secondary cell and a load and the charge control FET connected between the discharge control FET and a charger in response to a detection signal from the charge/discharge monitoring circuit and a voltage of a negative electrode of the charger, and opening and closing the discharge path and the charge path. The control circuit turns off the discharge control FET and turns on the charge control FET, and then turns off the charge control FET when detecting that the voltage of the negative electrode of the charger reaches a predetermined voltage or higher.

Abstract: A reference current circuit includes: a current mirror circuit for supplying Iout based on Iin; an E-mode MOS including a drain that supplies Iout, a gate connected to the drain, and a grounded source; a first D-mode MOS including a gate terminal connected to the gate terminal of the E-mode MOS, and generating Vref; a voltage dividing circuit for supplying a divided voltage (Vdiv) of Vref; and a second D-mode MOS for supplying Iin based on Vdiv. The E-mode MOS is the same as the first D-mode MOS in conductivity type and impurity concentration of a channel, and is different from the first D-mode MOS in Fermi level of a gate electrode. The voltage dividing circuit supplies Vdiv higher than a threshold voltage of the second D-mode MOS and lower than a cross point (X) to a gate terminal of the second D-mode MOS.

Abstract: A reference voltage circuit includes a differential amplifier circuit capable of stably operating at a constant voltage even if a collector voltage of an NPN transistor changes with temperature and is received. A voltage adjustment circuit is included between commonly connected sources and commonly connected back gates of a first PMOS transistor and a second PMOS transistor serving as input ports of a differential amplifier circuit. A voltage generated by the voltage adjustment circuit is configured to adjust a source-back gate voltage of the first PMOS transistor and the second PMOS transistor in accordance with a voltage change in which the collector voltage of the NPN transistor received at one of the input ports of the differential amplifier circuit.

Abstract: A voltage regulator includes an output transistor which outputs an output voltage to an output port; a dividing resistor which divides an adjustment voltage input to a voltage adjustment port and outputs a feedback voltage; a first reference voltage circuit which outputs a first reference voltage; an error amplifier circuit which controls a gate voltage of the output transistor based on the first reference voltage and the feedback voltage; and a ground fault protection circuit which, upon monitoring the adjustment voltage and detecting the voltage adjustment port having a ground fault, increases the feedback voltage to the first reference voltage.

Abstract: A current detection circuit includes: an input port, an output port; a rectifying element; a current control circuit; a load element, a first transistor, which is a first conductivity type field effect transistor; and a voltage detection circuit including a voltage detection terminal and a detection result output port. The current control circuit includes a first terminal, connected to a first power source terminal, and a second terminal, connected to an anode terminal of the rectifying element, a drain of the first transistor, and the voltage detection terminal of the voltage detection circuit. A gate of the first transistor is configured to connect the input port and a cathode terminal of the rectifying element to a second power source terminal via the load element. The output port is connected to the detection result output port of the voltage detection circuit.

Abstract: An electrostatic protection circuit and a semiconductor device include: a first diode whose anode is connected to a signal terminal; a second diode whose cathode is connected to a cathode of the first diode and whose anode is connected to a GND terminal; and a depletion type MOS transistor connected in parallel with the first diode.

Abstract: An electronic device with a boost circuit includes: a first capacitor including a first terminal connected to an input terminal and a second terminal connected to a reference potential terminal; a first rectification element; a second capacitor including a first terminal connected to the first terminal of the first capacitor through the first rectification element and a second terminal connected to the reference potential terminal; a voltage detection circuit including a voltage detection terminal connected to the first terminal of the second capacitor and a detection signal output terminal; and a boost circuit including a detection signal input terminal connected to the detection signal output terminal, a boost power input terminal connected to the first terminal of the first capacitor, and a boost power output terminal connected to a node between the first terminal of the second capacitor and the voltage detection terminal.

Abstract: A power generation sensor, generating electric power using a liquid, includes: a base; a positive electrode for power generation disposed in a first direction of the base and containing a first material; a negative electrode for power generation disposed in the first direction and containing a second material; a first connector electrode connected to a one-side end of the positive electrode in the first direction and to a sensor module; and a second connector electrode connected to a one-side end of the negative electrode in the first direction and to the sensor module. The first connector electrode contains the first material and has a larger width in a second direction orthogonal to the first direction than the positive electrode in the second direction. The second connector electrode contains the second material and has a larger width in the second direction than the negative electrode in the second direction.

Abstract: Provided is a charge/discharge control circuit controllable by a control signal from a controller that is external. The charge/discharge control circuit includes a control circuit configured to, in response to a power-down control signal for transitioning to a power-down state being input from the controller, latch the power-down control signal and block a discharge path from a secondary cell (SC) to the controller.

Abstract: A voltage monitoring device 2 includes: a comparator circuit 31; a state determination circuit 32; a pulse pattern setting circuit 33; an output circuit 36; a VDD port 21; a VSS port 22; an input port 24; and an output port 23. The comparator circuit 31 is connected to the state determination circuit 32. The state determination circuit 32 is connected to the pulse pattern setting circuit 33. The pulse pattern setting circuit is connected to the output port 23 via the output circuit 36.

Abstract: There is provided a high withstand voltage LDMOS field-effect transistor that enables the compatibility of an increase of its withstand voltage and a decrease of its ON resistance.

Abstract: The present invention provides a ?? AD converter and a sensor device having a small circuit scale and high conversion accuracy. A ?? AD converter includes a ?? AD modulator, an accumulator, a counter, an adjustment value storage part, a first adder, a cumulative value latch part, and a control circuit. The control circuit outputs to the adjustment value storage part a signal designating a temperature range according to the adjustment cumulative value received from the first adder in a case where the count value received from the counter reaches a predetermined value. The adjustment value storage part outputs the adjustment value of the offset value and the adjustment value of the count value according to the signal to the first adder and the counter. The control circuit outputs the latch signal to the cumulative value latch part in response to completion of counting by the counter.