Abstract: In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration.
Abstract: A clock signal boost circuit includes a first NMOS transistor having a drain to a power terminal, a source to a first node, and a gate to a first terminal, a second NMOS transistor having a drain to the first node, a source to a GND, and a gate to a second terminal, a third NMOS transistor having a drain to the power terminal, a source to a second node, and a gate to the second terminal, a capacitor between the first node and the second node, a PMOS transistor having a source to the second node, a drain to an output terminal, and a gate to the second terminal, and a fourth NMOS transistor having a drain to the output terminal, a source to the GND, and a gate to the second terminal. The first and the third NMOS transistors are depletion type NMOS transistors.
Abstract: A second source portion having an impurity concentration lower than that of a first source portion, both forming a source region, includes a first sub-portion having a depth from a bottom surface of the first source portion down to a second height higher than a first height, and a second sub-portion having an upper surface in contact with a part of a bottom surface of the first sub-portion, one side surface in a second direction perpendicular to a first direction in contact with an outer side surface of the trench, another side surface in the second direction, both side surfaces in the first direction, and a bottom surface in contact with the base layer, and having a depth from a bottom surface of the first sub-portion up to at least the first height.
Abstract: A charge/discharge control circuit includes: a first power supply terminal connected to a first electrode of a secondary battery; a second power supply terminal connected to a second electrode of the secondary battery; a charge control terminal connected to a discharge control switch and a charge control switch; a detection terminal; a control circuit; and an output circuit configured to output a charge control signal from the charge control terminal, and configured to output a first voltage when a charger is connected and the control circuit permits charging, and to output a voltage of the detection terminal which differs from the first voltage when the charger is connected and the control circuit prohibits charging. The output circuit is capable of outputting a voltage of the second power supply terminal which differs from the first voltage when the charger is not connected.
Abstract: A power feeding system has a power receiving device having: a resonant circuit having a receiving coil, a resonant capacitor configured to resonate with the receiving coil, and a first switching element configured to change an electrical connection state of the resonant capacitor; and a resonance control unit configured to control the first switching element, and has a power feeding device having: a second switching element connected in series to a feeding coil; a drive signal generation unit configured to generate a drive signal for driving the feeding coil; a variation detection unit configured to detect the change in electrical connection state of the resonant capacitor; and a power feeding control unit configured to control electric power supplied to the feeding coil based on a period of the resonant state and a period of the non-resonant state that are estimated from the periodic waveform variation.
Abstract: There are provided a charge/discharge control circuit and a battery apparatus to which a load having a large capacitance is connected. In the battery apparatus, the charge/discharge control circuit includes an overdischarge latch circuit providing an overdischarge latch signal, based on a discharge control signal supplied thereto and a voltage of an external negative voltage input terminal, and a logic circuit supplied with an overdischarge detection signal and the overdischarge latch signal and providing the overdischarge detection signal to a control circuit while receiving the overdischarge latch signal, to thereby enable the power supply to the load to stop in a short processing time.
Abstract: A constant current circuit includes a first current mirror circuit connected to a first power supply and having a first input transistor and a first output transistor of a first conductivity type, a second current mirror circuit having a second output transistor of a second conductivity type provided between the first input transistor and a second power supply, and a second input transistor of the second conductivity type provided between the first output transistor and the second power supply, a resistor interposed between the second output transistor and the second power supply, and a capacitor having one end connected to the first power supply and the other end connected to a connecting point of the second output transistor and the resistor.
Abstract: Provided are a charge/discharge control circuit capable of using an FET having a low withstand voltage. The charge/discharge control circuit is configured to control charging and discharging of a secondary cell, and includes: a positive power supply terminal and a negative power supply terminal for monitoring a voltage of the secondary cell; a charge control terminal configured to connect to a gate of a charge control FET, the charge control FET having one end connected to an external negative terminal to which a negative electrode of a load or a charger is connected; and a clamp circuit configured to clamp a signal at a high level for turning on the charge control FET to a voltage that is higher than a reference voltage by a predetermined voltage, the reference voltage being a voltage at the external negative terminal, the signal being output to the charge control terminal.
Abstract: To provide a bandgap reference circuit capable of shortening a start time at power-on in a circuit lowered in power consumption. There is provided a bandgap reference circuit using an op amplifier to generate a reference voltage, which is equipped with a first current source connected between a power supply terminal and an operating current input terminal of the op amplifier, a second current source having one end connected to the power supply terminal, and a switch connected between the other end of the second current source and the operating current input terminal of the op amplifier, and in which a switch is turned on at power-on and turned off after starting of the reference voltage.
Abstract: A power supply circuit including an input terminal, an output terminal, a power output circuit, and a mode selection circuit. In the power supply circuit, the mode selection circuit is configured to supply a signal indicating whether the power output circuit is operated as a charge pump-type power output circuit or a series regulator-type power output circuit, and a voltage applied from the input terminal is stepped up or down by the power output circuit and then provided to the output terminal.
Abstract: A charge and discharge control circuit operates between a first and a second power supply voltage of the secondary battery, and is used in a cascade-connection to the second charge and discharge control circuit having the same configuration, and includes an output circuit and an output terminal for discharge control, an input circuit and an input terminal for discharge control, and a control circuit. The input circuit includes a first MOS transistor having a source terminal connected to the input terminal and a gate terminal for receiving the first power supply voltage, a second MOS transistor having a drain terminal and a gate terminal connected to a drain terminal of the first MOS transistor and a source terminal for receiving the second power supply voltage, and a third MOS transistor current-mirror-connected to the second MOS transistor and having a drain terminal for supplying a discharge control input signal.
Abstract: Provided is an switching regulator including: an error amplification circuit configured to output a first error voltage based on an output voltage and a first reference voltage; a PFM comparison circuit configured to compare the first error voltage with a second reference voltage to output a comparison result signal; an oscillation circuit configured to output a clock signal, and to stop output of the clock signal depending on the comparison result signal; a frequency characteristics separation circuit to which the first error voltage is provided, and from which a second error voltage is supplied; a phase compensation circuit connected to the frequency characteristics separation circuit; and a PWM conversion circuit configured to turn the switching element on and off at a desired pulse width, based on the second error voltage and on the output from the oscillation circuit.
Abstract: A semiconductor device includes a multilayer wiring structure on a substrate. The multilayer wiring structure includes: a top wiring; a fuse element, which is located on a lower layer-side of the top wiring, and is made of metal having a melting point that is higher than that of the top wiring; and a lower-layer wiring, which is connected to each of ends of the fuse element. Provided is a semiconductor device in which fuse elements made of the high-melting point metal are arranged at high density.
Abstract: A comparator includes a first constant current source, a first transistor having a drain connected to the first constant current source, a gate connected to a non-inverted input terminal, and a source connected to an inverted input terminal, a second constant current source connected between the inverted input terminal and a second power supply terminal, a second transistor having a source connected to a first power supply terminal, a gate connected to the drain of the first transistor, and a drain connected to an output terminal, and a third constant current source connected between the drain of the second transistor and the second power supply terminal. An oscillation circuit includes comparators in which at least one of the comparators is a comparator described above.
Abstract: There is provided a constant current circuit having a current characteristic satisfactory in a high voltage circuit while being low in manufacturing cost. The constant current circuit includes a high breakdown-voltage depletion type NMOS transistor and a low breakdown-voltage depletion type NMOS transistor connected in series between a first terminal and a second terminal. The low breakdown-voltage depletion type NMOS transistor includes a first depletion type NMOS transistor and a second depletion type NMOS transistor connected in series. The high breakdown-voltage depletion type NMOS transistor has a gate connected to a connecting point of the first depletion type NMOS transistor and the second depletion type NMOS transistor.
Abstract: Provided is a resin-encapsulated semiconductor device in which heat dissipation characteristic and mounting strength to a substrate are improved. Heat dissipation outer leads connected to inner leads connected to the four corners of a die pad are exposed to the outside of an encapsulating resin to improve the heat dissipation characteristic. The ends of the heat dissipation outer leads are cut in lead frame pressing, and exterior plating films are formed on the entire surfaces of the heat dissipation outer leads including the ends in exterior plating of the resin-encapsulated semiconductor device, permitting easy formation of solder fillet when the semiconductor device is mounted on a substrate.
Abstract: Provided is a method of manufacturing a semiconductor device with which a trench shape having vertical, flat, and smooth side wall surfaces can be formed even at room temperature. A semiconductor substrate is placed on a sample stage which is kept at room temperature in a reaction container. A trench is formed in the semiconductor substrate by plasma etching that uses etching gas including oxygen and sulfur hexafluoride, while controlling the gas ratio of oxygen to sulfur hexafluoride so that the gas ratio is from 70% to 100%.
Abstract: In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time.
Abstract: An oscillation circuit small in circuit scale and in the influence of temperature on its oscillation frequency is provided. The oscillation circuit includes: a constant current circuit configured to supply a current based on a first depletion MOS transistor; a charge/discharge circuit having a first capacitor, a second capacitor, a second depletion MOS transistor, and a third depletion MOS transistor provided in a current path for charging the second capacitor, the first to third depletion MOS transistors having the same threshold voltage and the same temperature characteristics of the threshold voltage; and an RS latch circuit configured to output a waveform that falls by input of the reset signal and rises by input of the set signal.
Abstract: A magnetic sensor circuit includes: one of a first magnetic sensor element configured to output a voltage in accordance with a vertical magnetic field and a second magnetic sensor element configured to output a voltage in accordance with a horizontal magnetic field; a magnetic field signal processing circuit configured to output a signal in accordance with the voltage; at least three terminals capable of being connected to an external element, the at least three terminals being a first, a second, and a third terminal; a first wiring connecting the first terminal and the second terminal; and a second wiring connecting the first terminal and the third terminal in which one of the first magnetic sensor element and the second magnetic sensor element is arranged at a position where detection of a magnetic field generated by one of the first wiring and the second wiring is capable.