Abstract: Provided are an address determination circuit and a semiconductor device that improve accuracy of address determination with a simple circuit configuration. An address selection signal determination circuit receives a first determination signal based on a latched level of a serial data signal at first and second edge timings of an address selection signal, and a second determination signal based on a latched level of a serial clock signal at the first and second edge timings. The determination circuit determines the address selection signal is the serial clock signal in a case in which the first determination signal indicates false, determines the address selection signal is the serial data signal in a case in which the second determination signal indicates false, and determines the address selection signal is a power supply voltage based on its voltage in a case in which both determination signals indicate true.

Abstract: A current detection circuit includes: an input port, an output port; a rectifying element; a current control circuit; a load element, a first transistor, which is a first conductivity type field effect transistor; and a voltage detection circuit including a voltage detection terminal and a detection result output port. The current control circuit includes a first terminal, connected to a first power source terminal, and a second terminal, connected to an anode terminal of the rectifying element, a drain of the first transistor, and the voltage detection terminal of the voltage detection circuit. A gate of the first transistor is configured to connect the input port and a cathode terminal of the rectifying element to a second power source terminal via the load element. The output port is connected to the detection result output port of the voltage detection circuit.

Abstract: A current compensation circuit includes: a second bipolar transistor configured to have a same process variation as the first bipolar transistor; a first transistor including a drain connected to the emitter of the second bipolar transistor; a second transistor including a gate connected to a gate of the first transistor, and a drain connected to its own gate; a third transistor including a drain connected to the emitter of the first bipolar transistor, and a gate connected to the drain of the second transistor and each gate of the first and the second transistors; a constant current source; a fourth transistor including a drain connected to the base of the second bipolar transistor, and a gate connected to its own drain; and a fifth transistor including a drain connected to one end of the constant current source, and a gate connected to the gate of the fourth transistor.

Abstract: Provided is a sensor device being a signal processing device configured to supply a search signal so as to search for a direction in which a search target device is present. The signal processing device may include a directional antenna which has a variable direction, and is configured to wirelessly transmit electric power to the search target device; a transmission circuit configured to wirelessly transmit the search signal for searching for the search target device; and a detection circuit configured to receive a response signal transmitted from the search target device which has received the search signal, and to supply a detection signal corresponding to electric power of the response signal. The search signal may be transmitted in a direction in which the directional antenna having the variable direction is directed.

Abstract: A capacitive element 100 includes a P-type semiconductor substrate 110, a capacitor structure 150 formed above the P-type semiconductor substrate 110, and a shielding layer 130 formed between the P-type semiconductor substrate 110 and the capacitor structure 150 and electrically connected to the P-type semiconductor substrate 110. Preferably, a pair of electrodes 150a and 150b in the capacitor structure 150 are at a first potential V1 and a second potential V2 respectively, and the P-type semiconductor substrate 110 and the shielding layer 130 are at a third potential V3.

Abstract: A charge/discharge control circuit includes a control circuit configured to transition to a control state corresponding to a detection result of an abnormal state and perform open/close control of a charge/discharge path of one or a plurality of secondary batteries being a control target in accordance with the control state. The charge/discharge control circuit is connected in parallel to an external terminal provided in the charge/discharge path, and is configured to transmit and receive a detection result signal including the detection result to and from another charge/discharge control circuit having, as a control target, one or a plurality of secondary batteries different from the one or the plurality of secondary batteries of an own circuit, to thereby share the control state of the own circuit and the control state of the another charge/discharge control circuit.

Abstract: In order to enable generating an output logic signal having a duty cycle substantially equal to a duty cycle of an input logic signal, provided is a level shift circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a clamp circuit for limiting voltages of a first node and a second node within a range from a third voltage to a fourth voltage, and a waveform shaping circuit for providing an output logic signal based on level transitions of an input first logic signal and an input second logic signal in the same direction.

Abstract: A charge/discharge control circuit includes: a power supply terminal open detection circuit configured to provide an open detection result signal indicating a detection result of whether a power supply terminal connected to a semiconductor substrate is in an open state in which the power supply terminal is not externally connected; an overdischarge detection circuit configured to provide an overdischarge detection result signal indicating a detection result of whether a secondary battery is in an overdischarge state; a control circuit configured to control a charge/discharge path of the secondary battery; and an overdischarge mask circuit configured to mask an overdischarge detection signal provided from the overdischarge detection circuit to the control circuit in a case in which an open detection signal indicating that the open state is detected is provided.

Abstract: A semiconductor device capable of accurately compensating for a leakage current of an element which changes depending on a temperature environment. The semiconductor device includes: a current generation circuit configured to generate a charging current to be supplied to a capacitor connected to a connection terminal; and a current compensation circuit including a compensation current generation circuit configured to generate a compensation current which compensates for a leakage current from a compensation target element including one terminal connected to a path formed between an output terminal of the current generation circuit and the connection terminal, the current compensation circuit being configured to supply the generated compensation current to a point of connection to the path.

Abstract: Provided is a circuit or device suppressing an increase in circuit area. The overvoltage protection circuit is configured to protect first and second input transistors from overvoltage, the overvoltage protection circuit, including: a first transistor including one end connected to a drain of any one of the first input transistor and the second input transistor; a second transistor configured to supply a constant current to the one input transistor; a third transistor connected in cascade to the second transistor; a fourth transistor configured to supply a constant current to another input transistor; and a switch configured to establish conduction between the gate of the first input transistor and a drain of the second input transistor when a voltage exceeding a threshold voltage of the second input transistor is applied to the gate of each of the first input transistor and the second input transistor.

Abstract: A switching regulator includes a first differential amplifier outputting an amplified difference voltage obtained by amplifying a difference between a reference voltage and a feedback voltage in proportion to an output voltage; a second differential amplifier including a differential pair of a first transistor and a second transistor, the second differential amplifier outputting an error voltage based upon the amplified difference voltage supplied to each gate of the first transistor and the second transistor; a pulse wide modulation circuit converting the error voltage into a PWM signal; a first resistor containing a first end connected to the source of the first transistor; a second resistor containing a first end connected to the source of the second transistor; and a capacitor containing a first end connected to the source of the first transistor and the first end of the first resistor.

Abstract: A voltage regulator includes a differential amplifier circuit that controls an output transistor, and a phase compensation circuit. The phase compensation circuit includes: a first transistor having a drain connected to an output port of the differential amplifier circuit, and having a drain-source current with a negative temperature characteristic; a second transistor having a drain connected to a gate of the first transistor, having a gate connected to the gate of the first transistor via a resistor, and having a drain-source current with a negative temperature characteristic; and a current mirror circuit that includes a voltage detection transistor for detecting a voltage input to the gate of the output transistor, and that supplies a current with a positive temperature characteristic in response to a current flowing in the voltage detection transistor.

Abstract: The switching regulator includes a voltage regulator configured to supply an internal power supply voltage to a switching control circuit, a depletion type first transistor having a drain connected to an output terminal, a second transistor having a drain connected to a source of the first transistor and a source connected to the voltage regulator, and a comparison circuit comparing a source voltage of the first transistor with an output voltage of the voltage regulator. In response to detecting that the source voltage of the first transistor has become higher than the internal power supply voltage, control is performed so that the second transistor is turned on.

Abstract: The semiconductor device includes a first current generation circuit configured to generate a first current, a second current generation circuit configured to generate a second current from the first current, a third current generation circuit configured to generate a third current from the second current, a voltage-current conversion circuit configured to apply the third current to a diode and convert a generated voltage into a fourth current, a fourth current generation circuit configured to generate a fifth current from the fourth current, and an arithmetic circuit configured to generate a temperature signal from the fifth current.

Abstract: An oscillation circuit includes a ring oscillator and a waveform shape circuit configured to shape a waveform of an output signal of the ring oscillator. The waveform shape circuit includes: a preamplifier circuit configured to supply a first signal and a second signal which have the same frequency as a frequency of the output signal, the first signal having an opposite phase from a phase of the output signal, the second signal having an opposite phase from the phase of the first signal; and an amplitude amplifier circuit including a first transistor, a second transistor, a third transistor including a drain connected to a drain of the first transistor and a gate connected to a drain of the second transistor, and a fourth transistor including a drain connected to the drain of the second transistor and a gate connected to the drain of the first transistor.

Abstract: A reference current source 100 includes a reference voltage circuit 110, generating a reference voltage Vref; a voltage division circuit 130, dividing the reference voltage Vref and outputting a divided voltage Vdiv; and an output MOS transistor 140, supplying a reference current Iref in response to the divided voltage Vdiv being applied to a gate terminal 140G. The reference voltage circuit 110 includes a depletion type MOS transistor 111, and an enhancement type MOS transistor 112 having same conductivity type and impurity concentration as a channel 111c of the depletion type MOS transistor 111 and a different Fermi level from a gate electrode 111g of the depletion type MOS transistor 111. The voltage division circuit 130 outputs the divided voltage Vdiv within a voltage range which is 0V or above and lower than a cross point X to the gate terminal 140G of the output MOS transistor 140.

Abstract: A current limiter circuit limits a current in a path connecting an input terminal and an output terminal through a switch including a control port, the switch controlling the current to a predetermined value or less. The current limiter circuit includes a gate controller and a negative feedback circuit. The gate controller includes an input port which is connected to a connection point between a first path through which a first signal is transmitted and a second path through which a second signal is transmitted, and receiving the first signal and an output port supplying a control signal to the control port of the switch. The negative feedback circuit includes an input port coupled to a node via a capacitor if the capacitor is connected between thereof and the node provided between the switch and the output terminal and an output port connected to the input port.

Abstract: Provided are an environment sensor and an environment power generation device capable of measuring generated power of a power generation element to follow a changing environment. The environment sensor includes a voltage control circuit and a current measurement circuit. The voltage control circuit includes a voltage control terminal configured to receive a generated current and a current output terminal configured to provide an output current, and is configured to receive the generated current at the voltage control terminal while controlling a voltage of a positive electrode terminal of the power generation element connected to the voltage control terminal to a first predetermined voltage lower than a generated voltage of the power generation element. The current measurement circuit includes a current measurement terminal configured to receive the output current and a signal output terminal configured to provide a measurement signal.

Abstract: A controller includes: first to third input terminals; connection terminals; an output terminal; a first rectifying element, connected between the first input terminal and the second input terminal with a direction from the second input terminal to the first input terminal as a forward direction; a second rectifying element, connected between a connection point between the first input terminal and the first rectifying element and the output terminal with a direction from the connection point to the output terminal as a forward direction; an FET circuit, including a first depletion type FET and at least one other FET; a resistor, connected to the second input terminal and the third input terminal; and a clamp circuit, clamping a voltage of the third input terminal to a predetermined voltage.

Abstract: Provided is a sensor device being a signal processing device, including: a capacitor; a sensor unit configured to wirelessly transmit, in a case in which electric power of a predetermined amount or more is accumulated in the capacitor, a first signal (SG1) through use of the electric power accumulated in the capacitor; a reception unit configured to receive a radio wave transmitted from a power transmission device being an external device; and a transmission antenna functioning as a second transmission unit, the transmission antenna being configured to wirelessly transmit, in response to reception of the radio wave, a response signal (SG3) being a second signal generated based on the received radio wave without using the electric power accumulated in the capacitor.