Patents Assigned to ABLIC INC.
  • Patent number: 12625012
    Abstract: A temperature sensor device is capable of measuring minute temperature changes while being manufactured at low cost without needing a high performance IC tester. A temperature sensor device includes a temperature sensor circuit 2 and a temperature sensor 1. The temperature sensor 1 includes a PN junction element 15 which is a temperature sensing element, a variable current source which supplies different forward currents of at least two values to the PN junction element 15 and a constant voltage source 16 which outputs a constant voltage having the same temperature properties as a forward voltage of the PN junction element 15.
    Type: Grant
    Filed: October 30, 2023
    Date of Patent: May 12, 2026
    Assignee: ABLIC Inc.
    Inventors: Tsutomu Tomioka, Tadakatsu Kuroda, Makoto Mitani, Naohiro Hiraoka
  • Patent number: 12619272
    Abstract: The present invention provides a reference voltage generation device which includes a constant current circuit outputting a constant current in response to an input voltage; a voltage generation circuit connected in series to the constant current circuit, using the constant current as an input current, and generating an output voltage based on the input current; and a reference voltage output port outputting the output voltage. In the constant current circuit, multiple depletion type MOS transistors are connected in series, the gate widths are the same, and the sum of the gate lengths is the total gate length of the constant current circuit. In the voltage generation circuit, multiple enhancement type MOS transistors are connected in series, the gate widths are the same, and the sum of the gate lengths is the total gate length of the voltage generation circuit.
    Type: Grant
    Filed: March 26, 2024
    Date of Patent: May 5, 2026
    Assignee: ABLIC Inc.
    Inventor: Satoshi Suzuki
  • Publication number: 20260121426
    Abstract: A cell balancing circuit and a battery device are provided. The cell balancing circuit controls cell balancing between a first battery cell that generates a first cell voltage and a second battery cell which is connected in series with the first battery cell and generates a second cell voltage. The cell balancing circuit includes: a first voltage divider circuit that outputs a first voltage divider voltage as an average voltage of the first battery cell and the second battery cell; a first differential voltage-to-current converter that discharges from the first battery cell a first cell balancing current generated according to a voltage difference obtained by subtracting the second cell voltage from the first voltage divider voltage; and a second differential voltage-to-current converter that discharges from the second battery cell a second cell balancing current generated according to the voltage difference with polarity reversed.
    Type: Application
    Filed: October 13, 2025
    Publication date: April 30, 2026
    Applicant: ABLIC Inc.
    Inventor: Yasuhiro MIYAMOTO
  • Publication number: 20260121640
    Abstract: A semiconductor device (1) includes power terminals (VDD, GND), a voltage detection circuit (11), transistors (12, 13, 14), a depletion transistor (15), a control circuit (16), input ports (12a, 14a) connected to an output port (11b), input ports (11a, 16b) connected to the power terminal (VDD), a source end (12b), input ports (11c, 16c) connected to the power terminal (GND), source ends (14c, 15c), a gate end (15a), a source end (13b) connected to a drain end (12c), a gate end (13a) connected to a drain end (13c), drain ends (14b, 15b), and an input port (16a). Even in the case where a power supply voltage input to the voltage detection circuit (11) is equal to or lower than a minimum operating voltage of the voltage detection circuit (11), a signal received by the input port (16a) of the control circuit (16) matches a potential of the input terminal (GND).
    Type: Application
    Filed: October 8, 2025
    Publication date: April 30, 2026
    Applicant: ABLIC Inc.
    Inventors: Toshio NOMURA, Tomoki HIKICHI
  • Publication number: 20260092885
    Abstract: A monitor is provided, which is capable of continuously monitoring a monitoring target in a batteryless and maintenance free manner even with a small storage capacity. The monitor is a device using, as a sensor, a thermal battery including a thermoelectric power generation element which outputs a voltage according to a temperature difference between a temperature of an atmosphere covering the monitoring target and a temperature of a contact part with the monitoring target.
    Type: Application
    Filed: September 8, 2025
    Publication date: April 2, 2026
    Applicant: ABLIC Inc.
    Inventor: Minoru SUDO
  • Publication number: 20260095101
    Abstract: A boost circuit receives a storage detection signal from a power storage voltage detection circuit in response to a power storage voltage of a power storage element becoming equal to or higher than a predetermined voltage. The boost circuit includes: a first boost part, including a first buffer circuit pair having small leakage current, in which in the case where the storage detection signal is received, a first boost operation is performed by the first buffer circuit pair driven by power stored in the power storage element and a first boost voltage is output; and a second boost part, including a second buffer circuit pair having large leakage current, in which in the case where the first boost voltage is received, by power stored in the power storage element being supplied to the second buffer circuit pair, a second boost operation is performed and a second boost voltage is generated.
    Type: Application
    Filed: August 17, 2025
    Publication date: April 2, 2026
    Applicant: ABLIC Inc.
    Inventor: Minoru SUDO
  • Patent number: 12578746
    Abstract: A voltage regulator includes: an output transistor containing a source connected to an input port and a drain connected to an output port; voltage dividing resistors which are connected between a voltage adjustment port and a ground port, divide an adjustment voltage received at the voltage adjustment port, and output a feedback voltage; a reference voltage circuit which outputs a reference voltage; an error amplifier circuit which controls a gate voltage of the output transistor based on the reference voltage and the feedback voltage; and a disconnection protection circuit which includes a first MOS transistor containing a source connected to the output port and a gate connected to the voltage adjustment port, and detects a disconnection of a bonding wire of the voltage adjustment port.
    Type: Grant
    Filed: October 7, 2024
    Date of Patent: March 17, 2026
    Assignee: ABLIC Inc.
    Inventor: Kaoru Sakaguchi
  • Patent number: 12529715
    Abstract: A current detection circuit includes: an input port; an output port; a rectifying element; a capacitor; a first first conductivity type MOS transistor; and a voltage detection circuit. The input port is connected to an anode terminal of the rectifying element, the drain terminal of the first first conductivity type MOS transistor, and a voltage detection terminal of the voltage detection circuit. A cathode terminal of the rectifying element is connected to a first terminal of the capacitor and a gate terminal of the first first conductivity type MOS transistor. A second terminal of the capacitor and a source terminal of the first first conductivity type MOS transistor are connected to a first power source terminal. A detection result output port of the voltage detection circuit 105 is connected to the output port.
    Type: Grant
    Filed: March 7, 2024
    Date of Patent: January 20, 2026
    Assignee: ABLIC Inc.
    Inventor: Fumiyasu Utsunomiya
  • Patent number: 12519487
    Abstract: A semiconductor device includes an input port, a pulse generation circuit, and a serial-parallel conversion circuit. The input port is connected to an input port of the pulse generation circuit and a data signal input port of the serial-parallel conversion circuit. A signal received at the input port is a start bit and a data signal. The pulse generation circuit includes a delay circuit. A clock signal output port of the pulse generation circuit is connected to a clock signal input port of the serial-parallel conversion circuit.
    Type: Grant
    Filed: February 28, 2024
    Date of Patent: January 6, 2026
    Assignee: ABLIC Inc.
    Inventor: Tadakatsu Kuroda
  • Patent number: 12499988
    Abstract: An ultrasonic probe includes a probe configured to receive an ultrasonic wave, a plurality of wireless communication devices, and processing circuitry configured to assign identification information to ultrasonic image data generated based on the ultrasonic wave, for identifying the ultrasonic image data; and cause each of the plurality of wireless communication devices to transmit in parallel the ultrasonic image data having the identification information assigned, to a terminal device.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: December 16, 2025
    Assignee: ABLIC INC.
    Inventors: Naoto Yoneda, Masaya Tamamura, Naoto Adachi, Hiroshi Kishi
  • Patent number: 12494707
    Abstract: A DC/DC converter is able to test an overcurrent detection circuit without damaging the circuit. The DC/DC converter includes: a high-side switch; an IV conversion element and a current detection transistor which are connected in parallel with the high-side switch; a low-side switch; an overcurrent detection circuit; and a control circuit which outputs a first signal from a first output port to the high-side switch, outputs a second signal from the second output port to the low-side switch, and outputs a third signal from a third output port to the current detection transistor. The DC/DC converter further includes a test port which controls the current detection transistor to be turned off in the case of testing the overcurrent detection circuit, and supplies a variable current to a connection point between the current detection transistor which is controlled to be turned off and the IV conversion element.
    Type: Grant
    Filed: March 1, 2024
    Date of Patent: December 9, 2025
    Assignee: ABLIC Inc.
    Inventor: Yoshiomi Shiina
  • Patent number: 12481302
    Abstract: Provided is a constant voltage circuit with which a variation of an output voltage in response to a sudden change of a power supply voltage is small. The constant voltage circuit includes: an ED-type reference voltage circuit including at least two depletion mode transistors and an enhancement mode transistor which are connected in series; a depletion mode transistor connected in series between the power supply terminal and the ED-type reference voltage circuit; a first output terminal or a second output terminal; and a power supply variation suppression circuit which is connected between a connection point and the ground terminal and which suppresses a variation of the power supply voltage. The power supply variation suppression circuit includes a detection circuit which detects whether there is a variation of the power supply voltage, and a pass transistor which is connected in parallel to the detection circuit.
    Type: Grant
    Filed: December 21, 2023
    Date of Patent: November 25, 2025
    Assignee: ABLIC Inc.
    Inventor: Kosuke Takada
  • Patent number: 12477761
    Abstract: A bipolar transistor is capable of reducing variations in electrical characteristics. A bipolar transistor 100 includes: a collector region 150 which is a predetermined region in a P-type semiconductor substrate 110; a base region 140 which is formed within the collector region 150 and is an N-type well region; a polysilicon 130 formed on the base region 140 via an insulating film 131 and having an outer periphery, as viewed in a plan view, in a rectangular ring shape; and a P-type emitter region 120 surrounded by the polysilicon 130 and formed within the base region 140. The polysilicon 130 includes an extension portion 130a extending inside a contact region 141 of the base region 140 and electrically connected to the base region 140.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: November 18, 2025
    Assignee: ABLIC Inc.
    Inventor: Kazuhiro Tsumura
  • Patent number: 12468326
    Abstract: Provided is a voltage regulator capable of suppressing a current consumption in a non-regulation state with a simple circuit configuration. The voltage regulator includes an output transistor supplying an output voltage based on a control voltage, an error amplifier circuit supplying an amplified signal obtained by amplifying a difference between a voltage based on the output voltage and a reference voltage, a common source amplifier circuit supplying the control voltage to the output transistor based on the amplified signal, and a non-regulation state detection circuit supplying a detection signal to the common source amplifier circuit. The common source amplifier circuit includes a current control circuit including a plurality of parallel paths connecting between a control terminal of the output transistor and a power supply terminal, the plurality of parallel paths including a path to be closed in the non-regulation state and a path to be opened in the non-regulation state.
    Type: Grant
    Filed: September 11, 2023
    Date of Patent: November 11, 2025
    Assignee: ABLIC INC.
    Inventors: Atsushi Haruyama, Yasuhiko Ogura, Teruo Suzuki
  • Patent number: 12461886
    Abstract: A serial communication interface device includes a converter, a transmitter, and a receiver. The converter generates a first signal and a second signal based on changes in a clock signal, and a third signal and a fourth signal based on changes in a data signal, converts into the clock signal and the data signal based on the first to the fourth signals, sets the transmission start signal in response to receiving the fourth signal during a period where the clock signal is a first level, and sets the transmission end signal in response to reception of the third signal after reception of the first signal. The transmitter converts the first to the fourth signals into a communication signal and transmits the communication signal to a communication line. The receiver converts the communication signal received from the communication line into the first to the fourth signals.
    Type: Grant
    Filed: March 1, 2024
    Date of Patent: November 4, 2025
    Assignee: ABLIC Inc.
    Inventor: Biao Shen
  • Patent number: 12458327
    Abstract: An ultrasonic device includes: oscillation elements to generate ultrasonic waves toward a subject, and generate voltages according to ultrasonic waves reflected by the subject; a switch to select voltages generated by a predetermined number of oscillation elements, from among the generated voltages; and semiconductor devices. Each semiconductor device includes: a first terminal to receive a second predetermined number of voltages different from voltages received by other semiconductor devices, among the selected voltages; a first adder to add data based on the second predetermined number of voltages; a second terminal to receive an addition result of data by the first adder of each of the other semiconductor devices; a second adder to add the addition results of the data received by the first adder and the data received by the second terminal; and an image generator to generate image data based on the addition result of the second adder.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: November 4, 2025
    Assignee: ABLIC INC.
    Inventors: Naoto Adachi, Naoto Yoneda, Masaya Tamamura
  • Publication number: 20250327885
    Abstract: A magnetic sensor circuit 100 includes: a Hall element 111, outputting a Hall voltage VH and an offset voltage VHos; a switch unit 120, setting the Hall voltage VH as an AC component and the offset voltage VHos as a DC component; a first DC cut filter 130, allowing the Hall voltage VH of the AC component to pass through and cutting off the offset voltage VHos of the DC component, and setting, to a predetermined common-phase voltage V3C, a common-phase voltage V2C; an amplifier circuit, amplifying a voltage in which an offset voltage VAMPos to the Hall voltage; a demodulation circuit, demodulating the Hall voltage VH of the AC component and modulating the offset voltage VAMPos of the DC component; and a low pass filter 160, allowing the Hall voltage VH of the DC component and cutting off the offset voltage VAMPos of the AC component.
    Type: Application
    Filed: January 14, 2025
    Publication date: October 23, 2025
    Applicant: ABLIC Inc.
    Inventors: Toshiyuki TSUZAKI, Taisuke ISHIZAWA
  • Patent number: 12444701
    Abstract: Provided is a semiconductor device. The semiconductor device includes a first circuit that includes a plurality of fixed resistance elements connected in series; a second circuit that includes a plurality of variable resistance elements connected in series and that is connected in series to the first circuit; a first cover portion that is provided on an upper layer side of the first circuit and that covers the first circuit; and a second cover portion that is provided on an upper layer side of the second circuit and that covers the second circuit. The first cover portion included two or more first metal films electrically connected, correspondingly, to units having any number of the fixed resistance elements, and the second cover portion includes a second metal film electrically connected to the plurality of the variable resistance elements.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: October 14, 2025
    Assignee: ABLIC Inc.
    Inventor: Shinjiro Kato
  • Patent number: 12445113
    Abstract: A low pass filter and a semiconductor device including the low pass filter are capable of quickly reaching a steady state upon power-on. The low pass filter includes a first first-conductivity-type MOS transistor, an electrostatic capacitor, a buffer circuit, a bias circuit, an input terminal, and an output terminal. The input terminal is connected to a source terminal of the first first-conductivity-type MOS transistor. A drain terminal of the first first-conductivity-type MOS transistor is connected to a first terminal of the electrostatic capacitor, the output terminal, and an input terminal of the buffer circuit. An output terminal of the buffer circuit is connected to an input terminal of the bias circuit. An output terminal of the bias circuit is connected to a gate terminal of the first first-conductivity-type MOS transistor.
    Type: Grant
    Filed: January 26, 2024
    Date of Patent: October 14, 2025
    Assignee: ABLIC Inc.
    Inventors: Hideyuki Sawai, Tadashi Kurozo
  • Publication number: 20250309846
    Abstract: Provided is an amplifier. An amplifier includes a differential amplifier; and a phase compensation circuit including an input port and an output port. The phase compensation circuit includes a transconductance amplifier including a first input port, a second input port, and an output port connected to an output node of the differential amplifier; and a high-pass filter (HPF) configured to pass, among signals output from the differential amplifier, a signal having a frequency at a specified frequency or higher and supply it to the first input port and the second input port.
    Type: Application
    Filed: February 23, 2025
    Publication date: October 2, 2025
    Applicant: ABLIC Inc.
    Inventors: Nao OTSUKA, Toshiyuki TSUZAKI, Minoru SANO