Abstract: A charge/discharge control circuit controls charging and discharging using a discharge control FET which opens and closes a discharge path and a charge control FET which opens and closes a charge path. The charge/discharge control circuit includes a charge/discharge monitoring circuit; and a control circuit, turning on and off the discharge control FET connected between a secondary cell and a load and the charge control FET connected between the discharge control FET and a charger in response to a detection signal from the charge/discharge monitoring circuit and a voltage of a negative electrode of the charger, and opening and closing the discharge path and the charge path. The control circuit turns off the discharge control FET and turns on the charge control FET, and then turns off the charge control FET when detecting that the voltage of the negative electrode of the charger reaches a predetermined voltage or higher.

Abstract: Operational instability is prevented without compromising the state transition speed. A mask control circuit is a circuit which generates a mask signal masking a control signal during a period in which a voltage level of a monitoring target terminal to be monitored is transitioning. The mask control circuit includes: a first input port which receives a signal supplied to the monitoring target terminal; a second input port which receives a signal representing the voltage level of the monitoring target terminal; a logic circuit which determines whether the voltage level of the monitoring target terminal is in transition based on signals received from the first input port and the second input port; and an output port which outputs a signal indicating a determination result of whether the voltage level of the monitoring target terminal is in transition as the mask signal.

Abstract: A voltage follower circuit includes a first MOS transistor which has a source connected to an input port, a second MOS transistor which has a source connected to an output port and has a gate and a drain connected to a gate of the first MOS transistor, a first constant current source connected between a drain of the first MOS transistor and a second power supply terminal, a second constant current source connected between the drain of the second MOS transistor and the second power supply terminal, and a depletion type third MOS transistor which has a gate connected to the drain of the first MOS transistor, has a drain connected to a first power supply terminal, and has a source connected to the output port.

Abstract: A reference current circuit includes: a current mirror circuit for supplying Iout based on Iin; an E-mode MOS including a drain that supplies Iout, a gate connected to the drain, and a grounded source; a first D-mode MOS including a gate terminal connected to the gate terminal of the E-mode MOS, and generating Vref; a voltage dividing circuit for supplying a divided voltage (Vdiv) of Vref; and a second D-mode MOS for supplying Iin based on Vdiv. The E-mode MOS is the same as the first D-mode MOS in conductivity type and impurity concentration of a channel, and is different from the first D-mode MOS in Fermi level of a gate electrode. The voltage dividing circuit supplies Vdiv higher than a threshold voltage of the second D-mode MOS and lower than a cross point (X) to a gate terminal of the second D-mode MOS.

Abstract: A current detection circuit includes: an input port, an output port; a rectifying element; a current control circuit; a load element, a first transistor, which is a first conductivity type field effect transistor; and a voltage detection circuit including a voltage detection terminal and a detection result output port. The current control circuit includes a first terminal, connected to a first power source terminal, and a second terminal, connected to an anode terminal of the rectifying element, a drain of the first transistor, and the voltage detection terminal of the voltage detection circuit. A gate of the first transistor is configured to connect the input port and a cathode terminal of the rectifying element to a second power source terminal via the load element. The output port is connected to the detection result output port of the voltage detection circuit.

Abstract: A reference voltage circuit includes a differential amplifier circuit capable of stably operating at a constant voltage even if a collector voltage of an NPN transistor changes with temperature and is received. A voltage adjustment circuit is included between commonly connected sources and commonly connected back gates of a first PMOS transistor and a second PMOS transistor serving as input ports of a differential amplifier circuit. A voltage generated by the voltage adjustment circuit is configured to adjust a source-back gate voltage of the first PMOS transistor and the second PMOS transistor in accordance with a voltage change in which the collector voltage of the NPN transistor received at one of the input ports of the differential amplifier circuit.

Abstract: A voltage regulator includes an output transistor which outputs an output voltage to an output port; a dividing resistor which divides an adjustment voltage input to a voltage adjustment port and outputs a feedback voltage; a first reference voltage circuit which outputs a first reference voltage; an error amplifier circuit which controls a gate voltage of the output transistor based on the first reference voltage and the feedback voltage; and a ground fault protection circuit which, upon monitoring the adjustment voltage and detecting the voltage adjustment port having a ground fault, increases the feedback voltage to the first reference voltage.

Abstract: An electrostatic protection circuit and a semiconductor device include: a first diode whose anode is connected to a signal terminal; a second diode whose cathode is connected to a cathode of the first diode and whose anode is connected to a GND terminal; and a depletion type MOS transistor connected in parallel with the first diode.

Abstract: An electronic device with a boost circuit includes: a first capacitor including a first terminal connected to an input terminal and a second terminal connected to a reference potential terminal; a first rectification element; a second capacitor including a first terminal connected to the first terminal of the first capacitor through the first rectification element and a second terminal connected to the reference potential terminal; a voltage detection circuit including a voltage detection terminal connected to the first terminal of the second capacitor and a detection signal output terminal; and a boost circuit including a detection signal input terminal connected to the detection signal output terminal, a boost power input terminal connected to the first terminal of the first capacitor, and a boost power output terminal connected to a node between the first terminal of the second capacitor and the voltage detection terminal.

Abstract: A power generation sensor, generating electric power using a liquid, includes: a base; a positive electrode for power generation disposed in a first direction of the base and containing a first material; a negative electrode for power generation disposed in the first direction and containing a second material; a first connector electrode connected to a one-side end of the positive electrode in the first direction and to a sensor module; and a second connector electrode connected to a one-side end of the negative electrode in the first direction and to the sensor module. The first connector electrode contains the first material and has a larger width in a second direction orthogonal to the first direction than the positive electrode in the second direction. The second connector electrode contains the second material and has a larger width in the second direction than the negative electrode in the second direction.

Abstract: Provided is a charge/discharge control circuit controllable by a control signal from a controller that is external. The charge/discharge control circuit includes a control circuit configured to, in response to a power-down control signal for transitioning to a power-down state being input from the controller, latch the power-down control signal and block a discharge path from a secondary cell (SC) to the controller.

Abstract: A voltage monitoring device 2 includes: a comparator circuit 31; a state determination circuit 32; a pulse pattern setting circuit 33; an output circuit 36; a VDD port 21; a VSS port 22; an input port 24; and an output port 23. The comparator circuit 31 is connected to the state determination circuit 32. The state determination circuit 32 is connected to the pulse pattern setting circuit 33. The pulse pattern setting circuit is connected to the output port 23 via the output circuit 36.

Abstract: There is provided a high withstand voltage LDMOS field-effect transistor that enables the compatibility of an increase of its withstand voltage and a decrease of its ON resistance.

Abstract: The present invention provides a ?? AD converter and a sensor device having a small circuit scale and high conversion accuracy. A ?? AD converter includes a ?? AD modulator, an accumulator, a counter, an adjustment value storage part, a first adder, a cumulative value latch part, and a control circuit. The control circuit outputs to the adjustment value storage part a signal designating a temperature range according to the adjustment cumulative value received from the first adder in a case where the count value received from the counter reaches a predetermined value. The adjustment value storage part outputs the adjustment value of the offset value and the adjustment value of the count value according to the signal to the first adder and the counter. The control circuit outputs the latch signal to the cumulative value latch part in response to completion of counting by the counter.

Abstract: A current limiter circuit limits a current in a path connecting an input terminal and an output terminal through a switch including a control port, the switch controlling the current to a predetermined value or less. The current limiter circuit includes a gate controller and a negative feedback circuit. The gate controller includes an input port which is connected to a connection point between a first path through which a first signal is transmitted and a second path through which a second signal is transmitted, and receiving the first signal and an output port supplying a control signal to the control port of the switch. The negative feedback circuit includes an input port coupled to a node via a capacitor if the capacitor is connected between thereof and the node provided between the switch and the output terminal and an output port connected to the input port.

Abstract: A sensor device includes: a sensor element, outputting a signal; a first determination circuit, outputting an initialization signal containing a signal level corresponding to a determination result as to whether detection of a physical quantity has matched two consecutive times; a second determination circuit, including a counter which is able to, while initializing a count value if the detection of the physical quantity does not occur two consecutive times, continue counting if the detection of the physical quantity occurs two consecutive times until a set number of times is reached, the second determination circuit outputting an output latch signal containing a signal level corresponding to whether a consecutive match occurs until the set number of times is reached; and an output register, switching a signal level of an output signal supplied to an output terminal according to a change in the signal level of the output latch signal.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, and a vertical Hall element provided on the semiconductor substrate. The vertical Hall element includes an impurity diffusion layer of a second conductivity type and three or more electrodes. The impurity diffusion layer is provided on the semiconductor substrate and has an impurity concentration which increases as a depth increases. The three or more electrodes are provided in a straight line on a surface of the impurity diffusion layer and are composed of an impurity region of the second conductivity type having a higher concentration than the impurity diffusion layer.

Abstract: A current detection device includes a main busbar and a semiconductor chip. A detected current flows through the main busbar. The semiconductor chip is spaced apart from the main busbar. The semiconductor chip includes a branch busbar, a detection part, and an output part. The branch busbar is connected in parallel with the main busbar. The detection part is arranged adjacent to the branch busbar and detects a first magnetic field generated based on a branch current flowing from the main busbar to the branch busbar. The output part calculates and outputs a current value based on the first magnetic field detected by the detection part.

Abstract: A serial communication interface device includes a converter, a transmitter, and a receiver. The converter generates a first signal and a second signal based on changes in a clock signal, and a third signal and a fourth signal based on changes in a data signal, converts into the clock signal and the data signal based on the first to the fourth signals, sets the transmission start signal in response to receiving the fourth signal during a period where the clock signal is a first level, and sets the transmission end signal in response to reception of the third signal after reception of the first signal. The transmitter converts the first to the fourth signals into a communication signal and transmits the communication signal to a communication line. The receiver converts the communication signal received from the communication line into the first to the fourth signals.

Abstract: A capacitive element 100 includes a P-type semiconductor substrate 110, a capacitor structure 150 formed above the P-type semiconductor substrate 110, and a shielding layer 130 formed between the P-type semiconductor substrate 110 and the capacitor structure 150 and electrically connected to the P-type semiconductor substrate 110. Preferably, a pair of electrodes 150a and 150b in the capacitor structure 150 are at a first potential V1 and a second potential V2 respectively, and the P-type semiconductor substrate 110 and the shielding layer 130 are at a third potential V3.