Abstract: A bipolar transistor is capable of reducing variations in electrical characteristics. A bipolar transistor 100 includes: a collector region 150 which is a predetermined region in a P-type semiconductor substrate 110; a base region 140 which is formed within the collector region 150 and is an N-type well region; a polysilicon 130 formed on the base region 140 via an insulating film 131 and having an outer periphery, as viewed in a plan view, in a rectangular ring shape; and a P-type emitter region 120 surrounded by the polysilicon 130 and formed within the base region 140. The polysilicon 130 includes an extension portion 130a extending inside a contact region 141 of the base region 140 and electrically connected to the base region 140.

Abstract: A sensor device includes: a sensor element, outputting a signal; a first determination circuit, outputting an initialization signal containing a signal level corresponding to a determination result as to whether detection of a physical quantity has matched two consecutive times; a second determination circuit, including a counter which is able to, while initializing a count value if the detection of the physical quantity does not occur two consecutive times, continue counting if the detection of the physical quantity occurs two consecutive times until a set number of times is reached, the second determination circuit outputting an output latch signal containing a signal level corresponding to whether a consecutive match occurs until the set number of times is reached; and an output register, switching a signal level of an output signal supplied to an output terminal according to a change in the signal level of the output latch signal.

Abstract: An ESD protection circuit is connected in parallel with an internal circuit operating at a predetermined operating voltage between a VDD terminal and a VSS terminal, and includes an NMOS transistor in which an N type high concentration drain region is connected to the VDD terminal and an N type high concentration source region is connected to the VSS terminal. A threshold voltage and a trigger voltage of a parasitic bipolar transistor of the NMOS transistor are higher than the operating voltage and lower than a breakdown voltage of the internal circuit and a breakdown voltage of a gate insulating film of the NMOS transistor.

Abstract: A voltage fluctuation detection circuit includes: a source voltage decrease detection circuit configured to detect a decrease in voltage of a first power supply which outputs a first voltage and to output the result of detection as a voltage decrease detection signal using a second voltage which is lower than the voltage of the first power supply; an erroneous detection prevention circuit configured to detect an increase in voltage of the first power supply and to output the result of detection as a voltage increase detection signal using the second voltage; and a transistor configured to mask outputting of the voltage decrease detection signal in a period in which the increase in voltage of the first power supply is being detected based on the voltage increase detection signal.

Abstract: A semiconductor element is mounted on a die pad, and electrode pads arranged at an outer circumference of a surface of the semiconductor element are electrically connected to leads by wires, respectively. The semiconductor element, the die pad, and the leads are covered with an encapsulating resin. The semiconductor element has an element region having a high sensitivity with respect to stress, and an element region having a relatively low sensitivity with respect to stress. A recessed portion is formed in a surface of the encapsulating resin at a position above the element region having a high sensitivity with respect to stress.

Abstract: An ESD protection circuit is connected between a VDD terminal and a Vss terminal and is connected in parallel with an internal circuit which operates at an operating voltage and is damaged at a damage voltage or higher to protect the internal circuit from electrostatic discharge. The ESD protection circuit includes ESD protection elements connected in series. The ESD protection elements are transistors, diode elements, or a combination thereof. A sum of current-voltage characteristics of the ESD protection elements at a voltage higher than the operating voltage is higher than the operating voltage and lower than the damage voltage, until reaching a discharge current value or higher capable of protecting the internal circuit.

Abstract: The present invention provides a small and thin semiconductor device. The semiconductor device flip-chip bonds a semiconductor chip 1 and a lead 6 via a metal bonding portion 5 and includes a sealing resin covering them. The metal bonding portion 5 is provided with a gold-rich bonding layer 5a on the side of a first electrode 3a of the semiconductor chip 1 and a gold-rich bonding layer 5b on the side of a second electrode 3b of the lead 6, and connection between the semiconductor chip 1 and the lead 6 is strengthened, so that the semiconductor device does not require an anchor portion.

Abstract: A charge and discharge control circuit includes an external terminal voltage input port, a positive electrode power supply terminal, a negative electrode power supply terminal, a detector and an external terminal voltage detector connected to the external terminal voltage input port, and a control circuit. The external terminal voltage input port is connected to an external terminal via an external resistor. The positive electrode power supply terminal and the negative electrode power supply terminal are respectively connected to positive and negative electrodes of a secondary cell. The detector outputs a power-down detection signal to the control circuit in a case where the external terminal voltage input port receives a power-down control signal according to turn-on of an external FET, and outputs a power-down release signal to the control circuit in a case where the external FET is turned off and a charger is connected to the external terminal.

Abstract: A current detection device includes a main busbar and a semiconductor chip. A detected current flows through the main busbar. The semiconductor chip is spaced apart from the main busbar. The semiconductor chip includes a branch busbar, a detection part, and an output part. The branch busbar is connected in parallel with the main busbar. The detection part is arranged adjacent to the branch busbar and detects a first magnetic field generated based on a branch current flowing from the main busbar to the branch busbar. The output part calculates and outputs a current value based on the first magnetic field detected by the detection part.

Abstract: Provided is a reference voltage circuit configured to supply a reference voltage in which a variation in voltage with respect to a variation in power supply voltage is suppressed. The reference voltage circuit includes a reference voltage generation circuit which includes an output line for supplying a generated reference voltage to an output terminal; and an output control circuit which includes an output transistor and a stabilization transistor, and is configured to control the supply of the reference voltage to the output terminal, the output transistor containing a gate to which a control voltage is to be provided, the stabilization transistor containing a gate to be connected to a source of the output transistor, and a source to be connected to a drain of the output transistor, and having a gate-source voltage that is equal to or more than a dram-source voltage in a saturation region of the output transistor.

Abstract: An overcurrent protection circuit configured to limit an output current flowing through an output transistor includes a sense transistor that provides a sense current proportional to the output current, a sense resistor through which the sense current flows, a current limiting circuit that detects a sense voltage generated by the sense resistor and controls a gate voltage of the output transistor, and a current correction circuit that provides the sense resistor with a corrected sense current added to the sense current based on a difference of voltage between a drain voltage of the output transistor and a drain voltage of the sense transistor.

Abstract: An oscillation circuit includes first and second constant current circuits, first and second switch circuits, first and second MOS transistors, and an output port. The first constant current circuit is connected to one port of a capacitor. The first MOS transistor has a gate and a drain connected to the second constant current circuit and a source connected to another port of the capacitor. The second MOS transistor has a gate connected to the gate of the first MOS transistor, and a drain connected to the one port of the capacitor. The second switch circuit is connected between a source of the second MOS transistor and a second power supply terminal. The output port outputs a signal based on a voltage of the one port. Turn-on and turn-off of the first and second switch circuits are controlled by the signal of the output port and an inverted signal.

Abstract: Provided is a water leakage detection device, including: a pair of metal electrodes containing a first end and a second end; a warning device connected to the first end of the pair of metal electrodes, and configured to issue a warning based on a potential difference between the pair of metal electrodes; and a power supply which is connected to the second end of the pair of metal electrodes, and configured to apply a voltage between the pair of metal electrodes.

Abstract: Provided is a semiconductor device capable of detecting an abnormal state in which two fuses are both short-circuited or cut. The semiconductor device includes: a trimming circuit having a first fuse and a second fuse connected in series; a current source circuit configured to supply current to the trimming circuit; and a determination circuit configured to determine whether a connection state or disconnect state of the first fuse and the second fuse are abnormal or not based upon signals derived from an output signal of the trimming circuit.

Abstract: A layout design support apparatus 100 determines, in a circuit element connected to a first external terminal P1 to which a first potential identification label is added, whether to short-circuit one terminal connected to the first external terminal P1 and another terminal based on a determination criterion according to element type information and breakdown voltage information, adds the first potential identification label to the circuit components on a path from the first external terminal P1 to the one terminal of the circuit element to identify a first equipotential region according to determining not to short-circuit, repeatedly performs determination for the circuit element connected to the another terminal and identifies the first equipotential region according to determining to short-circuit, and identifies a second equipotential region when receiving a second potential identification label to be added to a second external terminal P2.

Abstract: An electronic device with a boost circuit includes: a first capacitor including a first terminal connected to an input terminal and a second terminal connected to a reference potential terminal; a first rectification element; a second capacitor including a first terminal connected to the first terminal of the first capacitor through the first rectification element and a second terminal connected to the reference potential terminal; a voltage detection circuit including a voltage detection terminal connected to the first terminal of the second capacitor and a detection signal output terminal; and a boost circuit including a detection signal input terminal connected to the detection signal output terminal, a boost power input terminal connected to the first terminal of the first capacitor, and a boost power output terminal connected to a node between the first terminal of the second capacitor and the voltage detection terminal.

Abstract: A reference voltage circuit includes: a first and a second NPN transistor having a collector and a base shorted and diode-connected, the second NPN transistor having an emitter connected to a first potential node and operating at a higher current density; a first resistor connected in series with the first NPN transistor; a second resistor having one end connected to a circuit with the first NPN transistor and the first resistor connected in series; a third resistor having one end connected to the collector of the second NPN transistor; a connection point to which the other ends of the second and the third resistor are connected; an arithmetic amplifier circuit having an inverting input terminal, a non-inverting input terminal, and an output terminal respectively connected to the second resistor, the third resistor, and the connection point; and a current supply circuit connected to the collector of the first NPN transistor.

Abstract: Provided is a sensor having different sensitivities depending on the positions. A sensor 1 is a sensor for detecting the presence of a liquid, and includes a first electrode 11 and a second electrode 12. The first electrode and the second electrode each have a thread-like or band-like structure, and are arranged side by side in a direction intersecting a longitudinal direction. At least one of the first electrode and the second electrode includes a first portion 111 having a first surface area at a first position in the longitudinal direction, and includes a second portion 112 having a second surface area larger than the first surface area at a second position in the longitudinal direction different from the first position.

Abstract: An LDMOS transistor includes a P-type body region formed on a main surface of a semiconductor substrate, an N-type source region, an N-type drift region, an N-type drain region, a gate electrode formed via a gate insulating film, a first field plate formed on the drift region via a first insulating film, a plurality of second field plates being in contact with the source region or the gate electrode and formed on the first field plate via a second insulating film, a P-type first buried region, and a P-type second buried region having an impurity concentration lower than an impurity concentration of the first buried region. Distances of the first and second field plates from the drain region in the semiconductor substrate plane direction decrease toward the upper layers, and have a predetermined relationship with the distances between the first and second buried regions and the drain region.

Abstract: A charge/discharge control circuit includes: an output terminal from which a cell-balance control signal is sent to each of the first and the second cell balance circuits; the first and the second voltage detection circuits; a control circuit configured to send the first and the second control signals in accordance with a detection signal received from at least one of the first and the second voltage detection circuits; and an output circuit configured to select one of a voltage of a power supply terminal, a voltage of an input terminal connected to each of a negative electrode of a first battery and a positive electrode of a second battery, and a voltage of a ground terminal in accordance with the first and second control signals, and send the selected voltage to the output terminal.