Abstract: Provided is a charge/discharge control circuit for controlling charging and discharging of a secondary cell. The charge/discharge control circuit includes a positive power supply terminal and a negative power supply terminal configured to monitor a voltage of the secondary cell, a charge control signal output terminal from which a charge control signal is output, the charge control signal controlling stopping and allowing charging of the secondary cell, a discharge control signal output terminal, an overcurrent detection terminal, an overcurrent cancel terminal, an external voltage input terminal provided separately from the overcurrent cancel terminal, a discharge overcurrent detection circuit connected to the overcurrent detection terminal, to which a discharge overcurrent detection voltage is set, and a discharge overcurrent cancel circuit connected to the overcurrent cancel terminal, to which a discharge overcurrent cancel voltage is set.

Abstract: In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time.

Abstract: A voltage-current conversion circuit includes a voltage-current conversion resistor connected to an input terminal, and a current mirror circuit which mirrors a current supplied from the voltage-current conversion resistor, wherein the current mirror circuit is constructed to include a depletion-type transistor whose source voltage is biased to be higher than the substrate voltage.

Abstract: A semiconductor device has inner leads (2a) of leads (2) which are covered with a first resin-encapsulating body (4), and has outer leads (2b) which are exposed from the first resin-encapsulating body (4), and which are given a shape bending downward and have distal ends having the bending shape extending in a lateral direction. The inner leads (2a) embedded in the first resin-encapsulating body (4) extend inward, and are then formed into a shape bending downward. Above end portions (3) having the bending shape, an element mounting portion (11) is formed of the first resin-encapsulating body (4), and a semiconductor element (6) placed on the element mounting portion (11) is covered with a second resin-encapsulating body (8).

Abstract: A magnetic substance detection sensor includes a support substrate, a semiconductor chip provided on the support substrate and having a magnetic field detection element, a permanent magnet provided on the support substrate, and a resin encapsulation layer covering the semiconductor chip and the permanent magnet. The resin encapsulation layer has a first resin layer exposing the permanent magnet and covering the semiconductor chip, and a second resin layer continuously covering the permanent magnet and the first resin layer, and stress caused by curing contraction of the second resin layer is smaller than that of the first resin layer.

Abstract: Provided is a backflow prevention circuit including a backflow prevention transistor as a p-channel MOS transistor interposed in series between an input terminal to which a power supply voltage is supplied, and an output-stage transistor as a p-channel MOS transistor, configured to supply an output voltage from an output terminal, and a backflow prevention control circuit configured to turn off the backflow prevention transistor if the output voltage exceeds the power supply voltage. The backflow prevention control circuit includes a first transistor, a first current source circuit, and a level shift circuit.

Abstract: A semiconductor device includes: a die pad; a semiconductor chip mounted on the die pad; a lead having an outer lead part and an inner lead par which is set up by a lead leg part extending from the outer lead part; an encapsulating resin sealing the die pad, the semiconductor chip, and the lead so that the lead is partially exposed; a support resin part provided on a bottom surface of the inner lead part, the support resin part being a portion of the encapsulating resin; and a notch part where the encapsulating resin is absent, and locating in a region surrounded by a bottom surface of the support resin part, an outer side surface of the outer lead part and an outer side surface of the lead leg part.

Abstract: The analog switch includes: a clock generation circuit configured to generate a first clock and a second clock; a transfer circuit including an NMOS transistor having a source and a back gate connected to each other, and a PMOS transistor having a source and a back gate connected to each other, one of which has a drain connected to the source of the other, and a source connected to a signal input terminal, and the other of which has a drain connected to a signal output terminal; a first control signal generation circuit configured to generate a control signal for switching the PMOS transistor based on a voltage at the signal input terminal and the first clock; and a second control signal generation circuit configured to generate a control signal for switching the NMOS transistor based on the voltage at the signal input terminal and the second clock.

Abstract: The semiconductor device includes a first vertical Hall element provided in a first region of a semiconductor substrate, and including a first plurality of electrodes arranged at predetermined intervals on a first straight line, a second vertical Hall element provided in a second region of the semiconductor substrate different from the first region, and including a second plurality of electrodes of the same number as that of the first plurality of electrodes, the second plurality of electrodes being arranged at the predetermined intervals on a second straight line parallel to the first straight line, a first drive power source configured to drive the first vertical Hall element, and a second drive power source configured to drive the second vertical Hall element and provided separately from the first drive power source.

Abstract: Provided is a booster circuit capable of adjusting a power conversion capacity in accordance with input power and also of stably performing a boost operation. The booster circuit includes a first voltage detection circuit configured to output as a first control signal a result of comparing an input voltage and a first voltage obtained by dividing an output voltage, a first oscillation circuit configured to be controlled to operate based on the first control signal, and a first switched-capacitor booster circuit configured to operate in accordance with a first clock signal provided from the first oscillation circuit.

Abstract: A hollow type semiconductor device has a pre-molded substrate (15) in which an element mounting portion, top surfaces of inner leads (2), and a top surface of frame-shaped wiring (7) are exposed on a first surface of a resin sealing body (6), and back surfaces of outer leads (3) and a back surface of a first frame-shaped wall (8) are exposed on a back surface of the resin sealing body (6). A hollow sealing body (14) including a second frame-shaped wall (9) and a sealing plate (4) is provided on the pre-molded substrate (15). The second frame-shaped wall (9) and the sealing plate (4) enclose a hollow portion (13) in which a semiconductor element (1) is kept.

Abstract: Provided is a semiconductor device capable of improving relative accuracy of semiconductor elements and a yield of a semiconductor integrated circuit device. The semiconductor device includes a flat region formed on a surface of a semiconductor substrate, and having an outer peripheral shape formed by regional sides and regional chamfer portions; an outer peripheral region surrounding the flat region, and having a uniform height different from a height of the flat region; a plurality of semiconductor elements having similar shapes or the same shape, and formed on the flat region; and a wiring metal connecting the plurality of semiconductor elements via contact holes formed in a second insulating film on the semiconductor elements.

Abstract: A differential amplifier circuit includes a first input transistor that receives a signal supplied from the first input terminal via a gate thereof, a second input transistor that receives a signal supplied from the second input terminal via a gate thereof, and an offset voltage adjustment circuit that is connected to at least one between the first input terminal and the gate of the first input transistor and between the second input terminal and the gate of the second input transistor.

Abstract: Provided is a Hall element which is reduced in asymmetrically generated offset voltage. A semiconductor device includes: a semiconductor layer of a first conductivity type having a Hall element forming region; an element isolation region of the first conductivity type having a concentration higher than a concentration of the semiconductor layer, the element isolation region being formed so as to surround the Hall element forming region; and a Hall element formed in the Hall element forming region and comprising a magnetism sensing portion of a second conductivity type which is higher in concentration than the semiconductor layer and which is kept apart from the element isolation region through the semiconductor layer.

Abstract: A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.

Abstract: A semiconductor device includes a first and a second vertical Hall elements formed parallel to each other. Each of the first and the second vertical Hall elements includes: a semiconductor layer on the semiconductor substrate; a Hall voltage output electrode and a first and a second drive current supply electrodes each formed of an impurity region, and sequentially arranged along a straight line on the semiconductor layer; and a first electrode isolation diffusion layer between the first drive current supply electrode and the Hall voltage output electrode, and a second electrode isolation diffusion layer between the Hall voltage output electrode and the second drive current supply electrode. The first and the second drive current supply electrodes each has the second depth deeper than the first depth of the Hall voltage output electrode and the depth of each of the electrode isolation diffusion layers.

Abstract: The constant current circuit includes a constant current generation circuit, a start-up detection circuit configured to detect start-up of the constant current generation circuit, and a clamp circuit configured to output a start-up voltage to the constant current generation circuit. The start-up voltage output from the clamp circuit is a voltage close to gate voltages that are higher than gate voltages of transistors that form a current mirror circuit of the constant current generation circuit, in a state where the constant current generation circuit is operating.

Abstract: A charge/discharge control circuit includes: a first power supply terminal connected to a first electrode of a secondary battery; a second power supply terminal connected to a second electrode of the secondary battery; a control circuit configured to control charge/discharge of the secondary battery; and a power-down release pulse generation circuit connected to the power-down release terminal, the power-down release pulse generation circuit being configured to supply, in a power-down state of the charge/discharge control circuit, a power-down release pulse at least to the control circuit in response to an input of a power-down release signal to the power-down release terminal to release the power-down state.

Abstract: A sensor device includes a detection electrode opposing an external electrode, and generating a voltage corresponding to a change in capacitance; a capacitive amplifier circuit having a first capacitor and a second capacitor, and configured to detect the voltage generated in the detection electrode, and output a detection signal obtained by amplifying the voltage generated in the detection electrode based on a capacitance ratio between the first capacitor and the second capacitor; a reset switch configured to reset the voltage of the detection electrode to a reference potential; a changeover switch configured to switch the capacitive amplifier circuit between a capacitive amplifier and a voltage follower; a second changeover switch configured to disconnect the first capacitor from the capacitive amplifier circuit; and a second reset switch configured to reset a voltage of the first capacitor to the reference potential.

Abstract: A test circuit includes a test pad supplied with a test signal causing the test circuit to be transitioned to a test mode, and further includes a first p channel MOS transistor having a source connected to the test pad, and a gate applied with a prescribed reference voltage, a first n channel MOS transistor having a drain connected to a drain of the first p channel MOS transistor, and a source grounded via a first current limiting element, and a control circuit which has an input terminal connected to the drain of the first n channel MOS transistor, and an output terminal connected to a gate of the first n Tr, and controls the first n channel MOS transistor from an on state to an off state when the test signal becomes a prescribed voltage or more.