Patents Assigned to Actel Corporation
  • Patent number: 8570819
    Abstract: A sense amplifier arrangement includes a first sense amplifier having a first input and a second input. A second sense amplifier has a first input and a second input. A switching circuit is configured to selectively couple the first input of the first sense amplifier to a first bit line in the array and the second input of the first sense amplifier to a first bit line in the array to selectively couple the first input of the first sense amplifier to the first bit line in the array, the first input of the second sense amplifier to the second bit line in the array, and the second inputs of the first and second sense amplifiers to a reference voltage.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: October 29, 2013
    Assignee: Actel Corporation
    Inventors: John McCollum, Fethi Dhaoui
  • Patent number: 8446170
    Abstract: A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: May 21, 2013
    Assignee: Actel Corporation
    Inventors: Joel Landry, Jonathan Greene, William C. Plants, Wenyi Feng
  • Patent number: 8415650
    Abstract: A resistive random access memory cell is formed on a semiconductor substrate. First and second diffused regions are disposed in the semiconductor substrate. A polysilicon gate is disposed above the first and second diffused regions. A first contact connects the first diffused region with a region of a first metal layer. A first interlayer dielectric layer is formed over the first metal layer and includes first and second vias, each including conductive plugs connected to the region of the first metal layer. First and second resistive random access memory devices formed over the first interlayer dielectric layer have first and second terminals, and include a dielectric layer and an ion source layer. The first terminals of the first and second resistive random access memory devices are coupled to the first metal layer by the first and second conductive plugs.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: April 9, 2013
    Assignee: Actel Corporation
    Inventors: Jonathan Greene, Frank W. Hawley, John McCollum
  • Patent number: 8320178
    Abstract: A memory cell includes a non-volatile p-channel transistor having a source coupled to a first potential, a drain, and a gate. A non-volatile n-channel transistor has a source coupled to a second potential, a drain, and a gate. A switch transistor has a gate coupled to a switch node, a source, and a drain. A stress transistor has a source and drain coupled between the drain of the non-volatile p-channel transistor and the drain of the non-volatile n-channel transistor, the stress transistor having a gate coupled to a gate bias circuit. Where one of the first or second potentials is a bit line, an isolation transistor is coupled between the other of the second potentials and one of the non-volatile transistors.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: November 27, 2012
    Assignee: Actel Corporation
    Inventor: John McCollum
  • Patent number: 8289047
    Abstract: An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs).
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: October 16, 2012
    Assignee: Actel Corporation
    Inventor: Benjamin S. Ting
  • Patent number: 8269204
    Abstract: A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: September 18, 2012
    Assignee: Actel Corporation
    Inventors: Jonathan Greene, Frank W. Hawley, John McCollum
  • Patent number: 8269203
    Abstract: A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: September 18, 2012
    Assignee: Actel Corporation
    Inventors: Jonathan Greene, Frank W. Hawley, John McCollum
  • Patent number: 8258811
    Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: September 4, 2012
    Assignee: Actel Corporation
    Inventors: Samuel W. Beal, Sinan Kaptanoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
  • Patent number: 8258567
    Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: September 4, 2012
    Assignee: Actel Corporation
    Inventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, Zhigang Wang
  • Patent number: 8255854
    Abstract: A method for reducing delay in an integrated circuit by compensating for differences in rise and fall delay times comprises creating a timing graph; computing minimum delay tuples for nodes in the timing graph; if there is not at least one feasible delay tuple, determining a longest path and computing minimum delay tuples for the longest path; changing polarities on the longest path to reduce delays; updating the timing graph by transferring new polarity and delay values; performing timing analysis to determine a new longest path if the new longest path is shorter than the prior longest path, accepting a resulting polarity selection and computing minimum delay tuples for the longest path; if the new longest path is not shorter than the prior longest path, accepting a resulting polarity selection and implementing changes in a user-program bitstream.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: August 28, 2012
    Assignee: Actel Corporation
    Inventors: Kai Zhu, Volker Hecht
  • Patent number: 8244791
    Abstract: A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: August 14, 2012
    Assignee: Actel Corporation
    Inventors: Volker Hecht, Marcel Derevlean, Jonathan Greene
  • Patent number: 8191021
    Abstract: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements. Provision is made for applying the method to logic designs implemented in programmable logic integrated circuit devices.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: May 29, 2012
    Assignee: Actel Corporation
    Inventor: Sana Rezgui
  • Patent number: 8120955
    Abstract: A push-pull non-volatile memory array includes memory cells with an n-channel non-volatile pull-down transistor in series with a p-channel volatile pull-up transistor. A non-volatile transistor row line is associated with each row of the array and is coupled to the control gates of each n-channel non-volatile pull-down transistor in the row. A volatile transistor row line is associated with each row of the array and is coupled to the control gates of each p-channel volatile pull-up transistor in the row with which it is associated. A column line is associated with each column in the array and is coupled to the source of each p-channel volatile pull-up transistor in the column with which it is associated.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: February 21, 2012
    Assignee: Actel Corporation
    Inventors: Zhigang Wang, Fethi Dhaoui, John McCollum, Vidyadhara Bellippady
  • Patent number: 8085064
    Abstract: A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: December 27, 2011
    Assignee: Actel Corporation
    Inventors: Wenyi Feng, Jonathan Greene
  • Patent number: 8067959
    Abstract: A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: November 29, 2011
    Assignee: Actel Corporation
    Inventors: William C. Plants, Suhail Zain, Joel Landry, Gregory W. Bakker, Tomek P. Jasinoski
  • Patent number: 8040151
    Abstract: A programmable logic device (PLD) adapted to enter a low-power or sleep mode with programmable wakeup pins in a wakeup group of pins is disclosed. Wake on a single pin change, wake on vector, and wake on a single pin transition are supported. The approach is to select the actively participating pins, enable the desired operation, define the wakeup condition, enter sleep mode, monitor the external signals coupled to the active pins, and exit sleep mode when the wakeup condition is detected.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: October 18, 2011
    Assignee: Actel Corporation
    Inventor: Theodore Speers
  • Publication number: 20110234258
    Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
    Type: Application
    Filed: June 10, 2011
    Publication date: September 29, 2011
    Applicant: ACTEL CORPORATION
    Inventors: Samuel W. Beal, Sinan Kaptonoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
  • Patent number: 7977970
    Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: July 12, 2011
    Assignee: Actel Corporation
    Inventors: Samuel W. Beal, Sinan Kaptanoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
  • Patent number: 7956404
    Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: June 7, 2011
    Assignee: Actel Corporation
    Inventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
  • Patent number: 7944238
    Abstract: A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: May 17, 2011
    Assignee: Actel Corporation
    Inventor: Sinan Kaptanoglu