Abstract: A system is provided that predicts motor wear and failures before they occur. Telemetry data from motors in a motor application is collected and predictive algorithms are used to determine when a motor is aging and when it may fail. Identifying a potential failure in these types of applications can help mitigate risk of other equipment failures and realize cost savings. In one example, a motor aging detection system is provided that includes one or more DC motors, and a motor controller coupled to each motor. The motor controller reads three phase currents from each motor and converts the phase currents to digital values, calculates telemetry data including applied voltages, back electric-motive force, inductance, and resistance of each motor at periodic intervals, stores this telemetry data for each motor in a memory. An age detection circuit retrieves this information from the memory and determines age factors of the motor.

Abstract: A system is provided that predicts motor wear and failures before they occur. Telemetry data from motors in a motor application is collected and predictive algorithms are used to determine when a motor is aging and when it may fail. Identifying a potential failure in these types of applications can help mitigate risk of other equipment failures and realize cost savings. In one example, a motor aging detection system is provided that includes one or more DC motors, and a motor controller coupled to each motor. The motor controller reads three phase currents from each motor and converts the phase currents to digital values, calculates telemetry data including applied voltages, back electric-motive force, inductance, and resistance of each motor at periodic intervals, stores this telemetry data for each motor in a memory. An age detection circuit retrieves this information from the memory and determines age factors of the motor.

Abstract: Methods and apparatus for selecting operating modes in a device are disclosed. In an embodiment, a method includes powering on a device that is configured to operate in safe and normal operating modes, detecting whether the device enters the normal operating mode within a time interval, and enabling the device to operate in the safe operating mode when the device does not enter the normal operating mode within the time interval. In an embodiment, an apparatus includes a power signal controller that powers on a device that is configured to operate in safe and normal operating modes, a state machine that detects whether the device enters the normal operating mode within a time interval, and a control signal controller that enables the device to operate in the safe operating mode when the device does not enter the normal operating mode within the time interval.

Abstract: A resonant charge pump circuit includes a resonant circuit having a bucket capacitor and a bucket inductor connected in series, and a switching circuit connected to the resonant circuit. The switching circuit switches to a first state that enables current to flow from an input terminal into the resonant circuit to charge the bucket capacitor and the bucket inductor, and switches to a second state that enables current to flow from the resonant circuit to discharge the bucket capacitor and the bucket inductor to an output terminal. The resonant circuit controls current flow into and out from the resonant circuit when the switching circuit switches between the states. The resonant charge pump circuit also includes a timing circuit that controls when the switching circuit switches between the states.

Abstract: A voltage regulator control integrated circuit includes constituent parts including an error amplifier circuit, a comparator circuit, a compensation signal generator circuit, an oscillator/one-shot circuit, a latch, and a current sense circuit. In a first example, the integrated circuit is operable in a first mode and in a second mode. In the first mode, the various parts are configured and interconnected in such a way that they operate together as a valley current mode regulator control circuit. In the second mode, the various parts are configured and interconnected in such a way that they operate together as a current-mode constant on-time mode regulator control circuit. In another example, a voltage regulator control integrated circuit has the same basic constituent parts and is operable in a first mode as a peak current mode regulator control circuit, or in a second mode as a constant off-time time mode regulator control circuit.

Abstract: A system comprises an integrated circuit package, an inductor that is part of a power supply, and a printed circuit board (PCB) having a metal trace disposed directly below the inductor when viewed from a top-down perspective. The integrated circuit package includes a first terminal, a second terminal, and a novel inductor current detection and calibration circuit. The first terminal is coupled to a first end of the metal trace and the second terminal is coupled to a second end of the metal trace. During operation of the power supply, the novel circuit detects an OCP condition whereby an output current of the power supply exceeds an OCP level. The novel circuit detects the OCP condition in part by sensing a voltage across the metal trace. After calibration at room temperature, the novel circuit performs accurate OCP detection over a range of temperatures without using any temperature sensor near inductor.

Abstract: An integrated circuit (IC) comprises a regulator circuit, a bootstrap control circuit, and a gate driver that drives a transistor pair in buck or boost mode to switch current through an inductor. The IC has a VIN terminal coupled to receive a voltage generated from an AC power source, a STR terminal coupled to receive a voltage from a stored power source (e.g., a capacitor bank), and a HSB terminal that is capacitively coupled to the inductor. When bucking or boosting, the regulator circuit generates VDD supply voltage from the stored power source, supplies the VDD supply voltage onto the bootstrap control circuit, and the bootstrap control circuit generates a gate driver supply voltage that is supplied to the gate driver circuit. When not bucking or boosting, voltage on the HSB terminal is maintained between a voltage threshold from the AC power source without draining the stored power source.

Abstract: An integrated circuit (IC) comprises a regulator circuit, a bootstrap control circuit, and a gate driver that drives a transistor pair in buck or boost mode to switch current through an inductor. The IC has a VIN terminal coupled to receive a voltage generated from an AC power source, a STR terminal coupled to receive a voltage from a stored power source (e.g., a capacitor bank), and a HSB terminal that is capacitively coupled to the inductor. When bucking or boosting, the regulator circuit generates VDD supply voltage from the stored power source, supplies the VDD supply voltage onto the bootstrap control circuit, and the bootstrap control circuit generates a gate driver supply voltage that is supplied to the gate driver circuit. When not bucking or boosting, voltage on the HSB terminal is maintained between a voltage threshold from the AC power source without draining the stored power source.

Abstract: An integrated circuit includes a gate driver circuit that controls high side and low side transistors to operate in buck or boost mode. In buck operating mode, after switching off the low side transistor, the gate driver circuit controls the high side transistor in a constant current mode. After the low side transistor is disabled and no longer conducts current, then the gate driver circuit controls the high side transistor to operate in full-enhancement mode. In boost operating mode, after switching off the high side transistor, the gate driver circuit controls the low side transistor in a constant current mode. After the high side transistor is disabled, then the gate driver circuit controls the low side switching transistor to operate in full-enhancement mode. In both buck and boost operation, the gate driver circuit operates without dead time in which both the high side and low side transistors are off.

Abstract: An integrated circuit includes a gate driver circuit that controls high side and low side transistors to operate in buck or boost mode. In buck operating mode, after switching off the low side transistor, the gate driver circuit controls the high side transistor in a constant current mode. After the low side transistor is disabled and no longer conducts current, then the gate driver circuit controls the high side transistor to operate in full-enhancement mode. In boost operating mode, after switching off the high side transistor, the gate driver circuit controls the low side transistor in a constant current mode. After the high side transistor is disabled, then the gate driver circuit controls the low side switching transistor to operate in full-enhancement mode. In both buck and boost operation, the gate driver circuit operates without dead time in which both the high side and low side transistors are off.

Abstract: An integrated circuit (IC) comprises a regulator circuit, a bootstrap control circuit, and a gate driver that drives a transistor pair in buck or boost mode to switch current through an inductor. The IC has a VIN terminal coupled to receive a voltage generated from an AC power source, a STR terminal coupled to receive a voltage from a stored power source (e.g., a capacitor bank), and a HSB terminal that is capacitively coupled to the inductor. When bucking or boosting, the regulator circuit generates VDD supply voltage from the stored power source, supplies the VDD supply voltage onto the bootstrap control circuit, and the bootstrap control circuit generates a gate driver supply voltage that is supplied to the gate driver circuit. When not bucking or boosting, voltage on the HSB terminal is maintained between a voltage threshold from the AC power source without draining the stored power source.

Abstract: A power loss protection integrated circuit includes a VIN terminal, a VOUT terminal, an STR terminal, a switch circuit (eFuse), a control circuit, and a prebiasing circuit. In a normal mode, current flows from a power source, into VIN, through the eFuse, out of VOUT, and to the output node. A switching converter of which the control circuit is a part is disabled. If a switch over condition then occurs, the eFuse is turned off and the switching converter starts operating. The switching converter receives energy from STR and drives the output node. Switch over is facilitated by prebiasing. Prior to switch over, the prebiasing circuit prebiases a control loop node as a function of eFuse current flow prior to switch over. When the switching converter begins operating, the node is already prebiased for the proper amount of current to be supplied by the switching converter onto the output node.

Abstract: A power loss protection integrated circuit includes a storage capacitor terminal (STR), an autonomous capacitor health check circuit, and a capacitor fault terminal (CF). The capacitor health check circuit autonomously performs periodic capacitor check operations. In a check operation, current is sinked from the STR terminal for a predetermined time and in a predetermined way. If during this time the voltage on the STR terminal STR drops below a predetermined voltage, then a digital signal CF is asserted onto the CF terminal. Immediately following each capacitor check, a charging voltage is driven onto the STR terminal to recharge the external capacitors coupled to the STR terminal. In one example, the integrated circuit further includes a current switch circuit (eFuse) and a buck/boost controller. The capacitor health check circuit is only enabled during normal mode operation of the integrated circuit, and the check circuit disables boost operation during capacitor checks.

Abstract: A power management integrated circuit includes pairs of high-side and low-side drivers, sensing circuitry, and a processor. The high-side and low-side drivers are used in combination with external discrete NFETs to drive multiple windings of a motor. The N-channel LDMOS transistor of each high-side driver has an associated isolation structure and a tracking and clamping circuit. If the voltage on a terminal of the integrated circuit pulses negative during a switching of current flow to the motor, then the isolation structure and tracking and clamping circuit clamps the voltage on the isolation structure and blocks current flow from the substrate to the drain. An associated ESD protection circuit allows the voltage on the terminal to pulse negative. As a result, a large surge of current that would otherwise flow through the high-side driver is blocked, and is conducted outside the integrated circuit through a body diode of an external NFET.

Abstract: A Dynamic Triggering and Sample Engine (DTSE) that detects a first trigger received on a trigger input terminal that triggers a series of analog-to-digital conversions to be completed by an analog-to-digital converter circuit. The DTSE then determines a first sequence configuration stored in a sequence configuration table that is associated with the first trigger, causes a first analog-to-digital conversion to be performed using the first sequence configuration; causes a first analog-to-digital conversion result value to be stored in a sequence result table; and outputs an interrupt to a processor indicating that the first analog-to-digital conversion result value is available in the sequence result table. The interrupt is output from the DTSE before all remaining analog-to-digital conversions in the series are completed. In response to receiving the interrupt, the processor reads the analog-to-digital result value from the sequence result table via a bus.

Abstract: A quality of charge (QoC) detector for use in inductive charging systems is disclosed. In an exemplary embodiment, an apparatus includes an inductor that receives a current signal to generate an electromagnetic field during a power transfer to an external device, and a quality detector to determine a quality metric associated with the power transfer. The apparatus also includes an indicator that indicates multiple states, where one of the multiple states is selected to indicate the quality metric.

Abstract: A voltage regulator control integrated circuit includes constituent parts including an error amplifier circuit, a comparator circuit, a compensation signal generator circuit, an oscillator/one-shot circuit, a latch, and a current sense circuit. In a first example, the integrated circuit is operable in a first mode and in a second mode. In the first mode, the various parts are configured and interconnected in such a way that they operate together as a valley current mode regulator control circuit. In the second mode, the various parts are configured and interconnected in such a way that they operate together as a current-mode constant on-time mode regulator control circuit. In another example, a voltage regulator control integrated circuit has the same basic constituent parts and is operable in a first mode as a peak current mode regulator control circuit, or in a second mode as a constant off-time time mode regulator control circuit.

Abstract: A DC-to-DC converter employs peak current mode control and includes a cycle skipping prevent circuit. If a latch is set, then a high side switch is turned on. A comparator receives a signal indicative of current flow and a compensated error signal. The prevent circuit supplies a delayed version of a low duty cycle, fixed frequency, oscillator signal onto the set input lead of the latch. The prevent circuit gates a high signal as output by the comparator onto the reset input lead of the latch. If the output of the comparator has, however, not transitioned high by a predetermined time, then the prevent circuit gates a high pulse onto the reset input lead. Accordingly, the prevent circuit ensures that the latch is reset once every period of the signal SET. A cycle skipping prevent circuit is also disclosed for use in a converter that employs valley current mode control.

Abstract: A system for authenticating a rechargeable battery and for detecting counterfeit batteries includes battery characteristics detection circuitry and a battery. Battery characteristics detection circuitry performs an authentication routine on the battery such that battery characteristics of the battery are measured. Battery characteristics include state of health, state of charge, internal resistance, relaxation time, and impedance. The battery is validated by comparing the battery characteristics to validation parameters provided by a manufacturer. If battery characteristics are within ranges of the validation parameters, then the battery is authenticated as originating from a particular manufacturer or batch. If validation fails, then the device is disabled or protected. In one example, validation parameters are stored and compared locally on a device. In another example, the device communicates battery characteristics to a remote entity that performs the validation.

Abstract: A DC-to-DC converter employs peak current mode control and includes a cycle skipping prevent circuit. If a latch is set, then a high side switch is turned on. A comparator receives a signal indicative of current flow and a compensated error signal. The prevent circuit supplies a delayed version of a low duty cycle, fixed frequency, oscillator signal onto the set input lead of the latch. The prevent circuit gates a high signal as output by the comparator onto the reset input lead of the latch. If the output of the comparator has, however, not transitioned high by a predetermined time, then the prevent circuit gates a high pulse onto the reset input lead. Accordingly, the prevent circuit ensures that the latch is reset once every period of the signal SET. A cycle skipping prevent circuit is also disclosed for use in a converter that employs valley current mode control.